From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Fri, 1 May 2020 12:55:51 +0000 (+0100)
Subject: arch-arm: Remove checkSveTrap method
X-Git-Tag: v20.1.0.0~652
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5aff442c76e538c85981d12d31a963780f9e4092;p=gem5.git

arch-arm: Remove checkSveTrap method

This is not part of the arm arm pseudocode and prevents a proper
fix of the checkSveEnabled

Change-Id: I075749095316e59e395d5b84a23db4309bdd7a92
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28767
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index b84aa810b..6da8b770e 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -984,37 +984,28 @@ ArmStaticInst::sveAccessTrap(ExceptionLevel el) const
 }
 
 Fault
-ArmStaticInst::checkSveTrap(ThreadContext *tc, CPSR cpsr) const
+ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
 {
     const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
+    if ((el == EL0 && cpacr.zen != 0x3) ||
+        (el == EL1 && !(cpacr.zen & 0x1)))
+        return sveAccessTrap(EL1);
 
     if (ArmSystem::haveVirtualization(tc) && el <= EL2) {
-        CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL2);
-        if (cptrEnCheck.tz)
+        CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL2);
+        if (cptr_en_check.tz)
             return sveAccessTrap(EL2);
     }
 
     if (ArmSystem::haveSecurity(tc)) {
-        CPTR cptrEnCheck = tc->readMiscReg(MISCREG_CPTR_EL3);
-        if (!cptrEnCheck.ez)
+        CPTR cptr_en_check = tc->readMiscReg(MISCREG_CPTR_EL3);
+        if (!cptr_en_check.ez)
             return sveAccessTrap(EL3);
     }
 
     return NoFault;
 }
 
-Fault
-ArmStaticInst::checkSveEnabled(ThreadContext *tc, CPSR cpsr, CPACR cpacr) const
-{
-    const ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el;
-    if ((el == EL0 && cpacr.zen != 0x3) ||
-        (el == EL1 && !(cpacr.zen & 0x1)))
-        return sveAccessTrap(EL1);
-
-    return checkSveTrap(tc, cpsr);
-}
-
-
 static uint8_t
 getRestoredITBits(ThreadContext *tc, CPSR spsr)
 {
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index ce6569a7a..bee39036b 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -475,11 +475,6 @@ class ArmStaticInst : public StaticInst
      */
     Fault sveAccessTrap(ExceptionLevel el) const;
 
-    /**
-     * Check an SVE access against CPTR_EL2 and CPTR_EL3.
-     */
-    Fault checkSveTrap(ThreadContext *tc, CPSR cpsr) const;
-
     /**
      * Check an SVE access against CPACR_EL1, CPTR_EL2, and CPTR_EL3.
      */