From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 15:04:58 +0000 (+0000)
Subject: correct syscon bus address to 0xC000_0000
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b0974dcb8dac795b8754de65c510667ad7a20d6;p=ls2.git

correct syscon bus address to 0xC000_0000
---

diff --git a/src/ls2.py b/src/ls2.py
index 49fc731..df3fb59 100644
--- a/src/ls2.py
+++ b/src/ls2.py
@@ -94,13 +94,13 @@ class DDR3SoC(SoC, Elaboratable):
         # System Configuration info
         self.syscon = MicrowattSYSCON(sys_clk_freq=clk_freq,
                                       has_uart=(uart_pins is not None))
-        self._decoder.add(self.syscon.bus, addr=0xc000000) # at 0xc000_0000
+        self._decoder.add(self.syscon.bus, addr=0xc0000000) # at 0xc000_0000
 
         # SRAM (read-writeable BRAM)
         self.ram = SRAMPeripheral(size=4096)
         self._decoder.add(self.ram.bus, addr=0x8000000) # SRAM at 0x8000_0000
 
-        # UART
+        # UART at 0xC000_2000
         if uart_pins is not None:
             self.uart = UART16550()
             umap = MemoryMap(addr_width=7, data_width=8, name="uart_map")