From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 3 Feb 2015 22:11:57 +0000 (+0100)
Subject: Skip blackbox modules in design->selected_modules()
X-Git-Tag: yosys-0.5~31
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b41470e151e3b1019e87dfddf900cea51922409;p=yosys.git

Skip blackbox modules in design->selected_modules()
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 9b55d4255..8c64217bb 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -460,7 +460,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_module(it.first))
+		if (selected_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
 			result.push_back(it.second);
 	return result;
 }
@@ -470,7 +470,7 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_whole_module(it.first))
+		if (selected_whole_module(it.first) && !it.second->get_bool_attribute("\\blackbox"))
 			result.push_back(it.second);
 	return result;
 }
@@ -480,7 +480,9 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const
 	std::vector<RTLIL::Module*> result;
 	result.reserve(modules_.size());
 	for (auto &it : modules_)
-		if (selected_whole_module(it.first))
+		if (it.second->get_bool_attribute("\\blackbox"))
+			continue;
+		else if (selected_whole_module(it.first))
 			result.push_back(it.second);
 		else if (selected_module(it.first))
 			log_warning("Ignoring partially selected module %s.\n", log_id(it.first));