From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Thu, 25 Jun 2020 10:28:48 +0000 (+0200)
Subject: Add bank address test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b4246e67db894916a6cb2f72ea1fccfec01396e;p=gram.git

Add bank address test
---

diff --git a/gram/test/test_dfii.py b/gram/test/test_dfii.py
index 7d4530c..f143867 100644
--- a/gram/test/test_dfii.py
+++ b/gram/test/test_dfii.py
@@ -52,3 +52,12 @@ class PhaseInjectorTestCase(FHDLTestCase):
             self.assertEqual((yield dfi.phases[0].address), 0xCDC)
 
         runSimulation(m, process, "test_phaseinjector.vcd")
+
+    def test_setbankaddress(self):
+        m, dfi, csrhost = self.generate_phaseinjector()
+
+        def process():
+            yield from wb_write(csrhost.bus, 0xC >> 2, 0xA8, sel=0xF)
+            self.assertEqual((yield dfi.phases[0].bank), 0xA8)
+
+        runSimulation(m, process, "test_phaseinjector.vcd")