From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 28 Sep 2020 15:53:23 +0000 (+0100)
Subject: connect SDRAM dqm to wrdata_mask
X-Git-Tag: 24jan2021_ls180~293
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b4254bea20b8562872cc94b889fd0e18e0a41e1;p=soc.git

connect SDRAM dqm to wrdata_mask
---

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 25da0a33..cd8119eb 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -224,11 +224,8 @@ class GENSDRPHY(Module):
         self.submodules.dq = SDRPad(pads, "dq", d.wrdata, d.wrdata_en, d.rddata)
 
         if hasattr(pads, "dm"):
-            # optimisation by yosys, fudge it... sigh
-            dm = Signal(len(pads.dm))
             for i in range(len(pads.dm)):
-                self.comb += dm[i].eq(1)
-                self.sync += pads.dm[i].eq(dm[i]) # FIXME
+                self.specials += SDROutput(i=d.wrdata_mask[i], o=pads.dm[i])
 
         # DQ/DM Control Path ----------------------------------------------
         rddata_en = Signal(cl + cmd_latency)