From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 27 Jun 2019 20:36:42 +0000 (+0100)
Subject: update to rst table format
X-Git-Tag: convert-csv-opcode-to-binary~4382
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b486bdfc14c9873b7dcc7c45bd3783bea9a620f;p=libreriscv.git

update to rst table format
---

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index 4c42e84fc..afe7fe559 100644
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -165,13 +165,10 @@ To support this option (where more complex implementations may skip some of thes
 
 The format is as follows:
 
-+--------+-------+-------+-------+-------+------+-------+-------+
 | 31:30  | 29    | 28:26 | 25:24 | 23:22 | 21   | 20:5  | 4:0   |
-+--------+-------+-------+-------+-------+------+-------+-------+
+|--------|-------|-------|-------|-------|------|-------|-------|
 | status | vlset | 16xil | pplen | rplen | mode | vlblk | opptr |
-+--------+-------+-------+-------+-------+------+-------+-------+
 | 2      | 1     | 3     | 2     | 2     | 1    | 16    | 5     |
-+--------+-------+-------+-------+-------+------+-------+-------+
 
 * status is the key field that effectively exposes the inner FSM (Finite State Machine) directly.
 * status = 0b00 indicates that the processor is not in "VBLOCK Mode". It is instead in standard RV Scalar opcode execution mode. The processor will leave this mode only after it encounters the beginning of a valid VBLOCK opcode.