From: Srivatsa Yogendra <36861801+srivatsa611y@users.noreply.github.com>
Date: Tue, 21 Aug 2018 20:14:07 +0000 (-0700)
Subject: Changing the register mstatus is read into (#152)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b4eb413c2620d4f29af1a8954871a74be8dee25;p=riscv-tests.git

Changing the register mstatus is read into (#152)

The mstatus reading overwrites the expected user mode cause value.
---

diff --git a/isa/rv64si/scall.S b/isa/rv64si/scall.S
index 0579806..82f202a 100644
--- a/isa/rv64si/scall.S
+++ b/isa/rv64si/scall.S
@@ -34,8 +34,8 @@ RVTEST_CODE_BEGIN
   # Otherwise, if in S mode, then U mode must exist and we don't need to check.
   li t0, MSTATUS_MPP
   csrc mstatus, t0
-  csrr t1, mstatus
-  and t0, t0, t1
+  csrr t2, mstatus
+  and t0, t0, t2
   beqz t0, 1f
 
   # If U mode doesn't exist, mcause should indicate ECALL from M mode.