From: Gabe Black Date: Wed, 1 Aug 2007 21:34:59 +0000 (-0700) Subject: X86: Hide the irrelevant portions of the address components for load and store microops. X-Git-Tag: m5_2.0_beta4~214 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b5e2fd6cdc4249fe31a1b7b45a224bbf2a88678;p=gem5.git X86: Hide the irrelevant portions of the address components for load and store microops. --HG-- extra : convert_revision : a5ac6fefa09882f0833537e23f1ac0477bc89bb9 --- diff --git a/src/arch/x86/insts/microldstop.cc b/src/arch/x86/insts/microldstop.cc index 9628256e4..9638a2ae3 100644 --- a/src/arch/x86/insts/microldstop.cc +++ b/src/arch/x86/insts/microldstop.cc @@ -64,16 +64,40 @@ namespace X86ISA const SymbolTable *symtab) const { std::stringstream response; + bool someAddr = false; printMnemonic(response, instMnem, mnemonic); - printDestReg(response, 0, dataSize); + if(flags[IsLoad]) + printDestReg(response, 0, dataSize); + else + printSrcReg(response, 2, dataSize); response << ", "; printSegment(response, segment); - ccprintf(response, ":[%d*", scale); - printSrcReg(response, 0, addressSize); - response << " + "; - printSrcReg(response, 1, addressSize); - ccprintf(response, " + %#x]", disp); + response << ":["; + if(scale != 0 && _srcRegIdx[0] != ZeroReg) + { + if(scale != 1) + ccprintf(response, "%d*", scale); + printSrcReg(response, 0, addressSize); + someAddr = true; + } + if(_srcRegIdx[1] != ZeroReg) + { + if(someAddr) + response << " + "; + printSrcReg(response, 1, addressSize); + someAddr = true; + } + if(disp != 0) + { + if(someAddr) + response << " + "; + ccprintf(response, "%#x", disp); + someAddr = true; + } + if(!someAddr) + response << "0"; + response << "]"; return response.str(); } }