From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Nov 2017 09:01:30 +0000 (+0100)
Subject: Accept real-valued delay values
X-Git-Tag: yosys-0.8~271
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b6e52118c09bb5967efc2bc2ebe53b9608bad89;p=yosys.git

Accept real-valued delay values
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index ec92f6628..3b9134797 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -359,6 +359,7 @@ package_body_stmt:
 non_opt_delay:
 	'#' TOK_ID { delete $2; } |
 	'#' TOK_CONSTVAL { delete $2; } |
+	'#' TOK_REALVAL { delete $2; } |
 	'#' '(' expr ')' { delete $3; } |
 	'#' '(' expr ':' expr ':' expr ')' { delete $3; delete $5; delete $7; };