From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 30 Sep 2019 21:38:06 +0000 (-0700)
Subject: Update mul test to DSP48E1
X-Git-Tag: working-ls180~990^2~13
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b7bc3ab85d31920883995636d26dc5b971ca24d;p=yosys.git

Update mul test to DSP48E1
---

diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys
index ec30c9c2c..f5306e848 100644
--- a/tests/xilinx/mul.ys
+++ b/tests/xilinx/mul.ys
@@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 12 t:LUT2
-select -assert-count 1  t:LUT3
-select -assert-count 6  t:LUT4
-select -assert-count 1  t:LUT5
-select -assert-count 33 t:LUT6
-select -assert-count 11 t:MUXCY
-select -assert-count 1  t:MUXF7
-select -assert-count 12 t:XORCY
-select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D
+select -assert-count 1 t:DSP48E1
+select -assert-none t:DSP48E1 %% t:* %D