From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 5 Apr 2020 20:03:07 +0000 (+0100)
Subject: add comment about form / op_fields
X-Git-Tag: div_pipeline~1460
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b7ff3820215fc43ad0d4aae601de536d7a997d8;p=soc.git

add comment about form / op_fields
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 5b5e3c11..5b6e158e 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -123,17 +123,22 @@ class ISACaller:
     def memassign(self, ea, sz, val):
         self.mem.memassign(ea, sz, val)
 
-    def prep_namespace(self):
+    def prep_namespace(self, formname, op_fields):
+        # TODO: get field names from form in decoder*1* (not decoder2)
+        # decoder2 is hand-created, and decoder1.sigform is auto-generated
+        # from spec
+        # then "yield" fields only from op_fields rather than hard-coded
+        # list, here.
         for name in ['SI', 'UI', 'D', 'BD']:
             signal = getattr(self.decoder, name)
             val = yield signal
             self.namespace[name] = SelectableInt(val, bits=signal.width)
 
     def call(self, name):
-        yield from self.prep_namespace()
-
         function, read_regs, uninit_regs, write_regs, op_fields, form \
             = self.instrs[name]
+        yield from self.prep_namespace(form, op_fields)
+
         input_names = create_args(read_regs | uninit_regs)
         print(input_names)