From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 25 Jul 2020 15:32:22 +0000 (+0100)
Subject: add CR0 regression, expected 0b10 actual 0b11
X-Git-Tag: semi_working_ecp5~544
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b897bd21bb250e09b254a3b2f188228622d9413;p=soc.git

add CR0 regression, expected 0b10 actual 0b11
---

diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 919c1859..58e5646f 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -103,7 +103,7 @@ class DivTestCases(unittest.TestCase):
         with Program(lst, bigendian) as prog:
             self.run_test_program(prog, initial_regs)
 
-    def test_8_regression(self):
+    def test_8_fsm_regression(self): # FSM result is "36" not 6
         lst = ["divwu. 3, 1, 2"]
         initial_regs = [0] * 32
         initial_regs[1] = 18
@@ -111,6 +111,14 @@ class DivTestCases(unittest.TestCase):
         with Program(lst, bigendian) as prog:
             self.run_test_program(prog, initial_regs)
 
+    def test_9_regression(self): # CR0 fails: expected 0b10, actual 0b11
+        lst = ["divw. 3, 1, 2"]
+        initial_regs = [0] * 32
+        initial_regs[1] = 1
+        initial_regs[2] = 0
+        with Program(lst, bigendian) as prog:
+            self.run_test_program(prog, initial_regs)
+
     def test_divw_by_zero_1(self):
         lst = ["divw. 3, 1, 2"]
         initial_regs = [0] * 32