From: Michael Nolan <mtnolan2640@gmail.com>
Date: Mon, 6 Apr 2020 13:26:02 +0000 (-0400)
Subject: Convert instruction info from tuple to namedtuple
X-Git-Tag: div_pipeline~1441
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b8b8682f22bb1b840e9dab93d728a900be03e9a;p=soc.git

Convert instruction info from tuple to namedtuple
---

diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py
index 245fa2f8..2bf47d5b 100644
--- a/src/soc/decoder/isa/caller.py
+++ b/src/soc/decoder/isa/caller.py
@@ -1,8 +1,13 @@
 from functools import wraps
 from soc.decoder.orderedset import OrderedSet
 from soc.decoder.selectable_int import SelectableInt, selectconcat
+from collections import namedtuple
 import math
 
+instruction_info = namedtuple('instruction_info',
+                              'func read_regs uninit_regs write_regs op_fields form asmregs')
+
+
 def create_args(reglist, extra=None):
     args = OrderedSet()
     for reg in reglist:
@@ -12,6 +17,7 @@ def create_args(reglist, extra=None):
         args = [extra] + args
     return args
 
+
 class Mem:
 
     def __init__(self, bytes_per_word=8):
@@ -154,11 +160,10 @@ class ISACaller:
     def call(self, name):
         # TODO, asmregs is from the spec, e.g. add RT,RA,RB
         # see http://bugs.libre-riscv.org/show_bug.cgi?id=282
-        fn, read_regs, uninit_regs, write_regs, op_fields, form, asmregs \
-            = self.instrs[name]
-        yield from self.prep_namespace(form, op_fields)
+        info = self.instrs[name]
+        yield from self.prep_namespace(info.form, info.op_fields)
 
-        input_names = create_args(read_regs | uninit_regs)
+        input_names = create_args(info.read_regs | info.uninit_regs)
         print(input_names)
 
         inputs = []
@@ -169,11 +174,11 @@ class ISACaller:
             print('reading reg %d' % regnum)
             inputs.append(self.gpr(regnum))
         print(inputs)
-        results = fn(self, *inputs)
+        results = info.func(self, *inputs)
         print(results)
 
-        if write_regs:
-            output_names = create_args(write_regs)
+        if info.write_regs:
+            output_names = create_args(info.write_regs)
             for name, output in zip(output_names, results):
                 regnum = yield getattr(self.decoder, name)
                 print('writing reg %d' % regnum)
diff --git a/src/soc/decoder/pseudo/pywriter.py b/src/soc/decoder/pseudo/pywriter.py
index e43cc41f..4b6b03ab 100644
--- a/src/soc/decoder/pseudo/pywriter.py
+++ b/src/soc/decoder/pseudo/pywriter.py
@@ -16,7 +16,7 @@ def get_isasrc_dir():
 header = """\
 # auto-generated by pywriter.py, do not edit or commit
 
-from soc.decoder.isa.caller import inject
+from soc.decoder.isa.caller import inject, instruction_info
 from soc.decoder.helpers import (EXTS, EXTS64, EXTZ64, ROTL64, ROTL32, MASK,)
 from soc.decoder.selectable_int import SelectableInt
 from soc.decoder.selectable_int import selectconcat as concat
@@ -26,10 +26,11 @@ class %s:
 
 """
 
-iinfo_template = """(%s, %s,
-                %s, %s,
-                %s, '%s',
-                %s)"""
+iinfo_template = """instruction_info(func=%s,
+                read_regs=%s,
+                uninit_regs=%s, write_regs=%s,
+                op_fields=%s, form='%s',
+                asmregs=%s)"""
 
 class PyISAWriter(ISA):
     def __init__(self):