From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 25 Jul 2016 14:37:58 +0000 (+0200)
Subject: Fixed a verilog parser memory leak
X-Git-Tag: yosys-0.7~160
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b944ef11b8964a00d833ad29c96ad46da06f7a3;p=yosys.git

Fixed a verilog parser memory leak
---

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index d1da630d5..4cb65a088 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -880,6 +880,7 @@ cell_port_list:
 			if (!node->children.empty()) break;
 			if (!node->str.empty()) break;
 			astbuf2->children.pop_back();
+			delete node;
 		}
 
 		// check port types