From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jan 2014 14:35:15 +0000 (+0100)
Subject: Added $bu0 cell to simlib.v
X-Git-Tag: yosys-0.2.0~162
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b96675696bb3001232b16a047cb2a9bbf8e3121;p=yosys.git

Added $bu0 cell to simlib.v
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 034244ca6..f3d652f0e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -53,6 +53,28 @@ assign Y = ~A_BUF.val;
 endmodule
 
 
+// --------------------------------------------------------
+
+module \$bu0 (A, Y);
+
+parameter A_SIGNED = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+`INPUT_A
+output [Y_WIDTH-1:0] Y;
+
+generate
+	if (!A_SIGNED && 0 < A_WIDTH && A_WIDTH < Y_WIDTH) begin:A
+		assign Y[A_WIDTH-1:0] = A_BUF.val;
+		assign Y[Y_WIDTH-1:A_WIDTH] = 0;
+	end else begin:B
+		assign Y = +A_BUF.val;
+	end
+endgenerate
+
+endmodule
+
 // --------------------------------------------------------
 
 module \$pos (A, Y);