From: Luke Kenneth Casson Leighton Date: Fri, 1 Jul 2022 15:00:45 +0000 (+0100) Subject: clarify branches early-exit X-Git-Tag: opf_rfc_ls005_v1~1421 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b977db21320a5a6fed53c3dbfab758d48919092;p=libreriscv.git clarify branches early-exit --- diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn index 59252d83f..5eb0a5716 100644 --- a/openpower/sv/branches.mdwn +++ b/openpower/sv/branches.mdwn @@ -75,9 +75,11 @@ NAND and NOR may be synthesised from AND and OR by inverting `BO[1]` which just leaves two modes: * Branch takes place on the **first** CR Field test to succeed - (a Great Big OR of all condition tests) + (a Great Big OR of all condition tests). Exit occurs + on the first **successful** test. * Branch takes place only if **all** CR field tests succeed: - a Great Big AND of all condition tests + a Great Big AND of all condition tests. Exit occurs + on the first **failed** test. Early-exit is enacted such that the Vectorised Branch does not perform needless extra tests, which will help reduce reads on @@ -103,7 +105,8 @@ has no special impact, regardless of whether the branch occurred or not. This can leave srcstep etc. in what may be considered an unusual state on exit from a loop and it is up to the programmer to -reset srcstep, dststep etc. to known-good values *(achieved with `setvl`)*. +reset srcstep, dststep etc. to known-good values +*(easily achieved with `setvl`)*. Additional useful behaviour involves two primary Modes (both of which may be enabled and combined):