From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 26 Sep 2019 20:59:05 +0000 (-0700)
Subject: Do not always zero out C (e.g. during cascade breaks)
X-Git-Tag: working-ls180~1039^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5b9deef10df2ab958112f6ff55f27776e492f187;p=yosys.git

Do not always zero out C (e.g. during cascade breaks)
---

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 5ccc47ba8..6ce5f2e16 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -24,8 +24,6 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-bool did_something;
-
 #include "passes/pmgen/xilinx_dsp_pm.h"
 #include "passes/pmgen/xilinx_dsp_CREG_pm.h"
 #include "passes/pmgen/xilinx_dsp_cascade_pm.h"
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index d4b4b8e22..714316808 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -40,11 +40,10 @@ finally
 		for (int i = 1; i < GetSize(longest_chain); i++) {
 			std::tie(dsp_pcin,P,AREG,BREG) = longest_chain[i];
 
-			dsp_pcin->setPort(ID(C), Const(0, 48));
-
 			if (i % MAX_DSP_CASCADE > 0) {
 				if (P >= 0) {
 					Wire *cascade = module->addWire(NEW_ID, 48);
+					dsp_pcin->setPort(ID(C), Const(0, 48));
 					dsp_pcin->setPort(ID(PCIN), cascade);
 					dsp->setPort(ID(PCOUT), cascade);
 					add_siguser(cascade, dsp_pcin);
@@ -65,9 +64,9 @@ finally
 				}
 				if (AREG >= 0) {
 					Wire *cascade = module->addWire(NEW_ID, 30);
+					dsp_pcin->setPort(ID(A), Const(0, 30));
 					dsp_pcin->setPort(ID(ACIN), cascade);
 					dsp->setPort(ID(ACOUT), cascade);
-					dsp_pcin->setPort(ID(A), Const(0, 30));
 					add_siguser(cascade, dsp_pcin);
 					add_siguser(cascade, dsp);
 
@@ -78,9 +77,9 @@ finally
 				}
 				if (BREG >= 0) {
 					Wire *cascade = module->addWire(NEW_ID, 18);
+					dsp_pcin->setPort(ID(B), Const(0, 18));
 					dsp_pcin->setPort(ID(BCIN), cascade);
 					dsp->setPort(ID(BCOUT), cascade);
-					dsp_pcin->setPort(ID(B), Const(0, 18));
 					add_siguser(cascade, dsp_pcin);
 					add_siguser(cascade, dsp);
 
@@ -97,7 +96,6 @@ finally
 			dsp = dsp_pcin;
 		}
 
-		did_something = true;
 		accept;
 	}
 endcode