From: Jacob Lifshay <programmerjake@gmail.com>
Date: Fri, 12 Mar 2021 22:50:01 +0000 (-0800)
Subject: autoformat code
X-Git-Tag: convert-csv-opcode-to-binary~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ba5374c0633c911c73770e37d2490e95c3daa98;p=soc.git

autoformat code
---

diff --git a/src/soc/decoder/power_decoder.py b/src/soc/decoder/power_decoder.py
index 81a80b8b..268a1ef1 100644
--- a/src/soc/decoder/power_decoder.py
+++ b/src/soc/decoder/power_decoder.py
@@ -92,7 +92,7 @@ from nmigen import Module, Elaboratable, Signal, Cat, Mux
 from nmigen.cli import rtlil
 from soc.decoder.power_enums import (Function, Form, MicrOp,
                                      In1Sel, In2Sel, In3Sel, OutSel,
-                                     SVEXTRA, SVEtype, SVPtype, # Simple-V
+                                     SVEXTRA, SVEtype, SVPtype,  # Simple-V
                                      RC, LdstLen, LDSTMode, CryIn,
                                      single_bit_flags, CRInSel,
                                      CROutSel, get_signal_name,
@@ -223,7 +223,7 @@ class PowerOp:
             if field not in power_op_csvmap:
                 continue
             csvname = power_op_csvmap[field]
-            print (field, ptype, csvname, row)
+            print(field, ptype, csvname, row)
             val = row[csvname]
             if csvname == 'upd' and isinstance(val, int):  # LDSTMode different
                 val = ptype(val)
diff --git a/src/soc/decoder/power_enums.py b/src/soc/decoder/power_enums.py
index f2a8595d..b8c7fe46 100644
--- a/src/soc/decoder/power_enums.py
+++ b/src/soc/decoder/power_enums.py
@@ -24,6 +24,7 @@ def find_wiki_dir():
     tabledir = join(tabledir, 'openpower')
     return join(tabledir, 'isatables')
 
+
 def find_wiki_file(name):
     filedir = os.path.dirname(os.path.abspath(__file__))
     basedir = dirname(dirname(dirname(filedir)))
@@ -63,6 +64,8 @@ def get_signal_name(name):
 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
 # is to process and guard the operation.  they are roughly divided by having
 # the same register input/output signature (X-Form, etc.)
+
+
 @unique
 class Function(Enum):
     NONE = 0
@@ -77,7 +80,7 @@ class Function(Enum):
     DIV = 1 << 9
     SPR = 1 << 10
     MMU = 1 << 11
-    SV = 1 << 12 # Simple-V https://libre-soc.org/openpower/sv
+    SV = 1 << 12  # Simple-V https://libre-soc.org/openpower/sv
 
 
 @unique
@@ -111,22 +114,25 @@ class Form(Enum):
     EVS = 26
     Z22 = 27
     Z23 = 28
-    SVL = 29 # Simple-V for setvl instruction
+    SVL = 29  # Simple-V for setvl instruction
 
 # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/
 
+
 @unique
 class SVPtype(Enum):
     NONE = 0
     P1 = 1
     P2 = 2
 
+
 @unique
 class SVEtype(Enum):
     NONE = 0
     EXTRA2 = 1
     EXTRA3 = 2
 
+
 @unique
 class SVEXTRA(Enum):
     NONE = 0
@@ -134,7 +140,8 @@ class SVEXTRA(Enum):
     Idx1 = 2
     Idx2 = 3
     Idx3 = 4
-    Idx_1_2 = 5 # due to weird BA/BB for crops
+    Idx_1_2 = 5  # due to weird BA/BB for crops
+
 
 @unique
 class SVP64PredMode(Enum):
@@ -142,6 +149,7 @@ class SVP64PredMode(Enum):
     INT = 1
     CR = 2
 
+
 @unique
 class SVP64PredInt(Enum):
     ALWAYS = 0
@@ -153,6 +161,7 @@ class SVP64PredInt(Enum):
     R30 = 6
     R30_N = 7
 
+
 @unique
 class SVP64PredCR(Enum):
     LT = 0
@@ -164,6 +173,7 @@ class SVP64PredCR(Enum):
     SO = 6
     NS = 7
 
+
 @unique
 class SVP64RMMode(Enum):
     NORMAL = 0
@@ -172,6 +182,7 @@ class SVP64RMMode(Enum):
     SATURATE = 3
     PREDRES = 4
 
+
 @unique
 class SVP64width(Enum):
     DEFAULT = 0
@@ -179,6 +190,7 @@ class SVP64width(Enum):
     EW_16 = 2
     EW_8 = 3
 
+
 @unique
 class SVP64subvl(Enum):
     VEC1 = 0
@@ -186,6 +198,7 @@ class SVP64subvl(Enum):
     VEC3 = 2
     VEC4 = 3
 
+
 @unique
 class SVP64sat(Enum):
     NONE = 0
@@ -217,7 +230,7 @@ _insns = [
     "popcntb", "popcntd", "popcntw", "prtyd", "prtyw", "rfid", "rldcl",
     "rldcr", "rldic", "rldicl", "rldicr", "rldimi", "rlwimi", "rlwinm",
     "rlwnm", "setb",
-    "setvl", # https://libre-soc.org/openpower/sv/setvl
+    "setvl",  # https://libre-soc.org/openpower/sv/setvl
     "sim_cfg", "slbia", "sld", "slw", "srad", "sradi", "sraw",
     "srawi", "srd", "srw", "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
     "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx", "sth", "sthbrx", "sthcx",
@@ -235,6 +248,8 @@ for i, insn in enumerate(_insns):
     asmidx[insn] = i
 
 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
+
+
 @unique
 class MicrOp(Enum):
     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
@@ -445,4 +460,4 @@ if __name__ == '__main__':
     for x in SPR:
         print(x, x.value, str(x), x.name)
 
-    print ("function", Function.ALU.name)
+    print("function", Function.ALU.name)