From: Chun-Chen TK Hsu <chunchenhsu@google.com>
Date: Tue, 23 Jul 2019 10:51:16 +0000 (+0800)
Subject: system-arm: Initialize ICC_SRE_EL3 register
X-Git-Tag: v19.0.0.0~706
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bb6210b10bf4a7a678dc41e6f7c9493842247b9;p=gem5.git

system-arm: Initialize ICC_SRE_EL3 register

Fast model CPU will throw exceptions if ICC_SRE_EL3 is not initialized
before accessing other interrupt controller system registers.

Change-Id: I638f77aa7a3a4ad92abf2554d039c37601fbd44f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19649
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
---

diff --git a/system/arm/aarch64_bootloader/boot.S b/system/arm/aarch64_bootloader/boot.S
index 589f38a4b..5e5e39439 100644
--- a/system/arm/aarch64_bootloader/boot.S
+++ b/system/arm/aarch64_bootloader/boot.S
@@ -90,6 +90,11 @@ _start:
         str	w0, [x1], #4
         str	w0, [x1], #4
 
+        /* SRE & Disable IRQ/FIQ Bypass & Allow EL2 access to ICC_SRE_EL2 */
+        mrs	x10, S3_6_C12_C12_5 // read ICC_SRE_EL3
+        orr	x10, x10, #0xf      // enable 0xf
+        msr	S3_6_C12_C12_5, x10 // write ICC_SRE_EL3
+        isb
 
 2:      mov	x0, #1
         msr	S3_0_c12_c12_6, x0 // ICC_IGRPEN0_EL1 Enable