From: lkcl <lkcl@web>
Date: Mon, 16 May 2022 18:09:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2191
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bb68af42499ca37aa9eb22b1a54b03199985608;p=libreriscv.git

---

diff --git a/openpower/sv/bitmanip.mdwn b/openpower/sv/bitmanip.mdwn
index d36b78f0e..fbedb496b 100644
--- a/openpower/sv/bitmanip.mdwn
+++ b/openpower/sv/bitmanip.mdwn
@@ -108,7 +108,7 @@ TODO: convert all instructions to use RT and not RS
 | NN |    |     |      |         | 10    011 |Rc| svstep |  SVL-Form     |
 | NN |    |     |      |         | 11    011 |Rc| setvl |   SVL-Form        |
 | NN |    |     |      |         | ----  110 |  | 1/2 ops | other table |
-| NN | RT | RA  | RB   | sh0-4   | sh5 1 111 |Rc| bmrevi |  TODO-Form    |
+| NN | RT | RA  | RB   | sh0-4   | sh5 1 111 |Rc| bmrevi |  MDS-Form    |
 
 ops (note that av avg and abs as well as vec scalar mask
 are included here [[sv/vector_ops]], and
@@ -416,7 +416,7 @@ uint_xlen_t bmextrev(RA, RB, sh)
 
 | 0.5|6.10|11.15|16.20|21.26| 27..30  |31| name   |
 | -- | -- | --- | --- | --- | ------- |--| ------ |
-| NN | RT | RA  | RB  | sh  | 1   011 |Rc| bmrevi |
+| NN | RT | RA  | RB  | sh  | 1111    |Rc| bmrevi |
 
 
 # grevlut