From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 18 Oct 2023 21:05:52 +0000 (+0100)
Subject: add expected results to "sc" instruction in TrapTestCase.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bc0468aa52168b9b50b0156661637f1620997fd;p=openpower-isa.git

add expected results to "sc" instruction in TrapTestCase.
this demonstrates how "sc" is meant to work in standard (system) mode.
this *may* be exactly what TestIssuer does, it will have to be checked
---

diff --git a/src/openpower/test/trap/trap_cases.py b/src/openpower/test/trap/trap_cases.py
index 704102d2..32b20125 100644
--- a/src/openpower/test/trap/trap_cases.py
+++ b/src/openpower/test/trap/trap_cases.py
@@ -55,11 +55,16 @@ class TrapTestCase(TestAccumulatorBase):
         lst = ["sc 0"]
         initial_regs = [0] * 32
         initial_regs[1] = 1
-        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678}
+        initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678} # to overwrite
+        # expected results: PC should be at 0xc00 (sc address)
         e = ExpectedState(pc=0xc00)
         e.intregs[1] = 1
+        e.sprs['SRR0'] = 4                  # PC to return to: CIA+4
+        e.sprs['SRR1'] = 0x9000000000022903 # MSR to restore after sc return
+        e.msr = 0x9000000000000001          # MSR changed to this by sc/trap
         self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
+                      initial_regs, initial_sprs,
+                      expected=e)
 
     def case_1_rfid(self):
         lst = ["rfid"]