From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Tue, 2 Aug 2022 17:27:34 +0000 (+0300)
Subject: power_enums: introduce RegType enum
X-Git-Tag: sv_maxu_works-initial~152
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bcaaa4c5c237df3df6e08573168de8ef2311a3f;p=openpower-isa.git

power_enums: introduce RegType enum
---

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 3886bab0..78015c36 100644
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -300,6 +300,34 @@ class SVP64LDSTmode(Enum):
     UNITSTRIDE = 3
 
 
+class RegType(Enum):
+    GPR = 0
+    RA = GPR
+    RB = GPR
+    RC = GPR
+    RS = GPR
+    RT = GPR
+
+    FPR = 1
+    FRA = FPR
+    FRB = FPR
+    FRC = FPR
+    FRS = FPR
+    FRT = FPR
+
+    CR_REG = 2
+    BF = CR_REG
+    BFA = CR_REG
+
+    CR_BIT = 3
+    BA = CR_BIT
+    BB = CR_BIT
+    BC = CR_BIT
+    BI = CR_BIT
+    BT = CR_BIT
+    BFT = CR_BIT
+
+
 # supported instructions: make sure to keep up-to-date with CSV files
 # just like everything else
 _insns = [