From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 19 Jul 2019 20:11:30 +0000 (-0700)
Subject: Add one more test with trimming Y_WIDTH of $sub
X-Git-Tag: working-ls180~1163^2~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bd088a686ce040c39a8353cf3a7cfe31581d635;p=yosys.git

Add one more test with trimming Y_WIDTH of $sub
---

diff --git a/tests/various/wreduce.ys b/tests/various/wreduce.ys
index f9e5ed4e3..8030c005e 100644
--- a/tests/various/wreduce.ys
+++ b/tests/various/wreduce.ys
@@ -9,7 +9,7 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
 select -assert-count 1 t:$add r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -21,8 +21,8 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
+##########
 
-### X - 0
 read_verilog <<EOT
 module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = j - (i << 4);
@@ -33,7 +33,7 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
 select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
@@ -45,9 +45,10 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-### 0 - X
+##########
+
 read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
+module wreduce_sub_test2(input [3:0] i, input [7:0] j, output [8:0] o);
     assign o = (i << 4) - j;
 endmodule
 EOT
@@ -56,7 +57,7 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
 select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
 
@@ -68,10 +69,11 @@ design -import gate -as gate
 miter -equiv -flatten -make_assert -make_outputs gold gate miter
 sat -verify -prove-asserts -show-ports miter
 
-### 0 - X
+##########
+
 read_verilog <<EOT
-module wreduce_sub_test1(input [3:0] i, input [7:0] j, output [8:0] o);
-    assign o = (i << 4) - j;
+module wreduce_sub_test3(input [3:0] i, input [7:0] j, output [8:0] o);
+    assign o = (j >> 4) - i;
 endmodule
 EOT
 
@@ -79,9 +81,10 @@ hierarchy -auto-top
 proc
 design -save gold
 
-prep
+prep # calls wreduce
 
-select -assert-count 1 t:$sub r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i
+dump
+select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
 
 design -stash gate