From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 4 Jun 2020 00:18:34 +0000 (+0100)
Subject: connect up Function Unit operand subsets
X-Git-Tag: div_pipeline~618
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bd1994d9d2ead01b41f129716832c449bf8d0b9;p=soc.git

connect up Function Unit operand subsets
---

diff --git a/src/soc/fu/compunits/compunits.py b/src/soc/fu/compunits/compunits.py
index c8e4a2bc..abca7a00 100644
--- a/src/soc/fu/compunits/compunits.py
+++ b/src/soc/fu/compunits/compunits.py
@@ -45,6 +45,7 @@ see:
 from nmigen import Elaboratable, Module
 from nmigen.cli import rtlil
 from soc.experiment.compalu_multi import MultiCompUnit
+from soc.decoder.power_enums import Function
 
 # pipeline / spec imports
 
@@ -105,18 +106,23 @@ class FunctionUnitBaseMulti:
 ###### actual Function Units: these are "single" stage pipelines #####
 
 class ALUFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.ALU
     def __init__(self): super().__init__(ALUPipeSpec, ALUBasePipe)
 
 class LogicalFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.LOGICAL
     def __init__(self): super().__init__(LogicalPipeSpec, LogicalBasePipe)
 
 class CRFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.CR
     def __init__(self): super().__init__(CRPipeSpec, CRBasePipe)
 
 class BranchFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.BRANCH
     def __init__(self): super().__init__(BranchPipeSpec, BranchBasePipe)
 
 class ShiftRotFunctionUnit(FunctionUnitBaseSingle):
+    fnunit = Function.SHIFT_ROT
     def __init__(self): super().__init__(ShiftRotPipeSpec, ShiftRotBasePipe)
 
 
diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 6423f61d..54e60864 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -39,6 +39,14 @@ class NonProductionCore(Elaboratable):
         regs = self.regs
         fus = self.fus.fus
 
+        # connect up instructions
+        for funame, fu in fus.items():
+            fnunit = fu.fnunit.value
+            enable = Signal(name="en_%s" % funame, reset_less=True)
+            comb += enable.eq(self.ivalid_i & (dec2.e.fn_unit & fnunit != 0))
+            with m.If(enable):
+                comb += fu.oper_i.eq_from_execute1(dec2.e)
+
         # enable-signals for each FU, get one bit for each FU (by name)
         fu_enable = Signal(len(fus), reset_less=True)
         fu_bitdict = {}