From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 10 Jun 2021 11:30:50 +0000 (+0100)
Subject: power shuffle, split SDRAM
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bda52634e887aba88cc55618384011fd64267e9;p=pinmux.git

power shuffle, split SDRAM
---

diff --git a/src/spec/ls180.py b/src/spec/ls180.py
index 763621f..dde9692 100644
--- a/src/spec/ls180.py
+++ b/src/spec/ls180.py
@@ -63,39 +63,43 @@ def pinspec():
     ps.vss("E", ('S', 1), 0, 0, 1)
     ps.vdd("I", ('S', 2), 0, 0, 1)
     ps.vss("I", ('S', 3), 0, 0, 1)
-    ps.sdram1("", ('S', 4), 0, 0, 21)
-    ps.mi2c("", ('S', 26), 0, 0, 2)
-    ps.vss("I", ('S', 28), 0, 1, 1)
-    ps.vdd("I", ('S', 29), 0, 1, 1)
-    ps.vss("E", ('S', 30), 0, 1, 1)
-    ps.vdd("E", ('S', 31), 0, 1, 1)
+    ps.mi2c("", ('S', 4), 0, 0, 2)
+    ps.sdram1("", ('S', 6), 0, 0, 15) # SDRAM DAM0, D0-7, AD0-3
+    ps.vss("I", ('S', 22), 0, 1, 1)
+    ps.vdd("I", ('S', 23), 0, 1, 1)
+    ps.vss("E", ('S', 24), 0, 1, 1)
+    ps.vdd("E", ('S', 25), 0, 1, 1)
+    ps.sdram1("", ('S', 26), 0, 15, 6) # AD4-9
 
-    ps.vdd("E", ('W', 0), 0, 2, 1)
-    ps.vss("E", ('W', 1), 0, 2, 1)
-    ps.vdd("I", ('W', 2), 0, 2, 1)
-    ps.vss("I", ('W', 3), 0, 2, 1)
-    ps.sdram2("", ('W', 4), 0, 0, 12)
-    ps.sdram1("", ('W', 16), 0, 21, 9)
-    ps.uart("0", ('W', 22), 0)
-    ps.mspi("0", ('W', 24), 0)
-    ps.vss("I", ('W', 28), 0, 3, 1)
-    ps.vdd("I", ('W', 29), 0, 3, 1)
-    ps.vss("E", ('W', 30), 0, 3, 1)
-    ps.vdd("E", ('W', 31), 0, 3, 1)
+    ps.sdram2("", ('W', 0), 0, 0, 4) # 1st 4, AD10-12,DQM1
+    ps.vdd("E", ('W', 4), 0, 2, 1)
+    ps.vss("E", ('W', 5), 0, 2, 1)
+    ps.vdd("I", ('W', 6), 0, 2, 1)
+    ps.vss("I", ('W', 7), 0, 2, 1)
+    ps.sdram2("", ('W', 8), 0, 4, 8) # D8-15
+    ps.sdram1("", ('W', 16), 0, 21, 9) # clk etc.
+    ps.vss("I", ('W', 22), 0, 3, 1)
+    ps.vdd("I", ('W', 23), 0, 3, 1)
+    ps.vss("E", ('W', 24), 0, 3, 1)
+    ps.vdd("E", ('W', 25), 0, 3, 1)
+    ps.uart("0", ('W', 26), 0)
+    ps.mspi("0", ('W', 28), 0)
 
-    ps.vss("I", ('E', 0), 0, 4, 1)
-    ps.vdd("I", ('E', 1), 0, 4, 1)
-    ps.vdd("I", ('E', 2), 0, 4, 1)
-    ps.vss("I", ('E', 3), 0, 4, 1)
-    ps.sys("", ('E', 4), 0, 5, 1) # analog VCO out in right top
-    ps.gpio("", ('E', 5), 0, 0, 8) # split GPIO 8-8
+    ps.sys("", ('E', 0), 0, 5, 1) # analog VCO out in right top
+    ps.gpio("", ('E', 1), 0, 0, 5) # GPIO 0-4
+    ps.vss("I", ('E', 6), 0, 4, 1)
+    ps.vdd("I", ('E', 7), 0, 4, 1)
+    ps.vdd("I", ('E', 8), 0, 4, 1)
+    ps.vss("I", ('E', 9), 0, 4, 1)
+    ps.gpio("", ('E', 10), 0, 5, 3) # GPIO 5-7
     ps.jtag("", ('E', 13), 0, 0, 4)
-    ps.gpio("", ('E', 17), 0, 8, 8) # the other 8 GPIO
-    ps.eint("", ('E', 25), 0, 0, 3)
-    ps.vss("I", ('E', 28), 0, 5, 1)
-    ps.vdd("I", ('E', 29), 0, 5, 1)
-    ps.vss("I", ('E', 30), 0, 5, 1)
-    ps.vdd("I", ('E', 31), 0, 5, 1)
+    ps.gpio("", ('E', 17), 0, 8, 5) # GPIO 8-12
+    ps.vss("I", ('E', 22), 0, 5, 1)
+    ps.vdd("I", ('E', 23), 0, 5, 1)
+    ps.vss("I", ('E', 24), 0, 5, 1)
+    ps.vdd("I", ('E', 25), 0, 5, 1)
+    ps.gpio("", ('E', 26), 0, 13, 3) # GPIO 13-15
+    ps.eint("", ('E', 29), 0, 0, 3)
 
     ps.vss("E", ('N', 6), 0, 6, 1)
     ps.vdd("E", ('N', 7), 0, 6, 1)
diff --git a/src/spec/pinfunctions.py b/src/spec/pinfunctions.py
index f921f2b..916a718 100644
--- a/src/spec/pinfunctions.py
+++ b/src/spec/pinfunctions.py
@@ -197,10 +197,10 @@ def sdram1(suffix, bank, n_adr=10):
         pname = "D%d*" % i
         buspins.append(pname)
         inout.append(pname)
-    for i in range(n_adr):
-        buspins.append("AD%d+" % i)
     for i in range(2):
         buspins.append("BA%d+" % i)
+    for i in range(n_adr):
+        buspins.append("AD%d+" % i)
     buspins += ['CLK+', 'CKE+', 'RASn+', 'CASn+', 'WEn+',
                 'CSn0+']
     return (buspins, inout, 'CLK')