From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 14 May 2020 07:59:38 +0000 (-0700)
Subject: opt_clean: improve warning message
X-Git-Tag: working-ls180~556^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5be4b00a0dad4c6fe281a0e925daeae26715f215;p=yosys.git

opt_clean: improve warning message
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 72ecc30e7..f7de02164 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -473,7 +473,7 @@ bool rmunused_module_init(RTLIL::Module *module, bool verbose)
 					goto next_wire;
 
 				if (mapped_wire_bit != init[i]) {
-					log_warning("Initial value conflict for wire '%s' and value '%s'.\n", log_signal(wire_bit), log_signal(mapped_wire_bit));
+					log_warning("Initial value conflict for %s resolving to %s but with init %s.\n", log_signal(wire_bit), log_signal(mapped_wire_bit), log_signal(init[i]));
 					goto next_wire;
 				}
 			}
diff --git a/tests/opt/opt_clean_init.ys b/tests/opt/opt_clean_init.ys
index bfc383955..0d567608d 100644
--- a/tests/opt/opt_clean_init.ys
+++ b/tests/opt/opt_clean_init.ys
@@ -1,4 +1,4 @@
-logger -expect warning "Initial value conflict for wire '\\y' and value '1'0'" 1
+logger -expect warning "Initial value conflict for \\y resolving to 1'0 but with init 1'1" 1
 logger -expect-no-warnings
 read_verilog <<EOT
 module top;