From: lkcl <lkcl@web>
Date: Wed, 23 Jun 2021 12:35:34 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~723
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5be5938b00a48f4e49c23fe94d63de9861283ae1;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index fd3fbed41..4b106928e 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -88,7 +88,8 @@ with the pseudocode below, the immediate can be used to give unit stride or elem
         if (RT.isvec) j++;
 
     # reverses the bitorder up to "width" bits
-    def bitrev(val, width):
+    def bitrev(val, VL):
+      width = log2(VL)
       result = 0
       for _ in range(width):
         result = (result << 1) | (val & 1)