From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 2 Sep 2020 11:44:15 +0000 (+0100)
Subject: add cmpl microwatt 1.bin test, cmpl
X-Git-Tag: semi_working_ecp5~217
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bf539a5ba6c651b6feefb187c840e6513dd664d;p=soc.git

add cmpl microwatt 1.bin test, cmpl
---

diff --git a/src/soc/fu/alu/test/test_pipe_caller.py b/src/soc/fu/alu/test/test_pipe_caller.py
index d059c70d..f03ef971 100644
--- a/src/soc/fu/alu/test/test_pipe_caller.py
+++ b/src/soc/fu/alu/test/test_pipe_caller.py
@@ -227,6 +227,26 @@ class ALUTestCase(TestAccumulatorBase):
         initial_regs[5] = 0xffffffffaaaaaaaa
         self.add_case(Program(lst, bigendian), initial_regs, {})
 
+    def case_cmpl_microwatt_0(self):
+        """microwatt 1.bin:
+           115b8:   40 50 d1 7c     .long 0x7cd15040 # cmpl 6, 0, 17, 10
+            register_file.vhdl: Reading GPR 11 000000000001C026
+            register_file.vhdl: Reading GPR 0A FEDF3FFF0001C025
+            cr_file.vhdl: Reading CR 35055050
+            cr_file.vhdl: Writing 35055058 to CR mask 01 35055058
+        """
+
+        lst = ["cmpl 6, 0, 17, 10"]
+        initial_regs = [0] * 32
+        initial_regs[0x11] = 0xffff6dc1
+        initial_regs[0xa] = 0
+        XER = 0xe00c0000
+        CR = 0x35055050
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                                initial_sprs = {'XER': XER},
+                                initial_cr = CR)
+
     def case_cmplw_microwatt_1(self):
         """microwatt 1.bin:
            10d94:   40 20 96 7c     cmplw   cr1,r22,r4