From: lkcl <lkcl@web>
Date: Wed, 25 May 2022 14:57:54 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2089
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5bfce5030656e4f88ca28976f6ad30d196cdc81c;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 86f219a10..bdb4b0fca 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -61,7 +61,7 @@ result.
         setvl target
         sv.addi/sm=1<<r3 t0, src1.v, 0 # copy src1[i]
         sv.cmpi src2.v, t0 # compare src2 vector to scalar
-        mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
+        sv.mfcrweird t1, cr0.v, eq # copy CR eq result bits to t1
         srr t1, t1, i # shift up by i before ORing
         or result, result, t1
         srr r3, r3, 1 # shift r3 predicate up by one