From: lkcl <lkcl@web>
Date: Sat, 29 Apr 2023 15:40:07 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c039a56dc2a8ac0b9aa1141c899754e897b46fa;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls016.mdwn b/openpower/sv/rfc/ls016.mdwn
index 0b858f25c..9b8f7ea0c 100644
--- a/openpower/sv/rfc/ls016.mdwn
+++ b/openpower/sv/rfc/ls016.mdwn
@@ -67,7 +67,8 @@ The number of uses for FFT is also equally known to be extremely high
 ARM has already added `vqrdmulhq_s16/32` instructions as their inclusion
 in any ISA replaces **eight** non-Twin-Butterfly instructions, which
 are often loop-unrolled, resulting in L1 I-Cache stripmining as well
-as requiring far greater resources or much more complex hardware to
+as requiring far greater resources (double the number of intermediate
+Vector registers) or much more complex hardware to
 get efficient execution.
 
 **Notes and Observations**: