From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 22:10:39 +0000 (-0700)
Subject: Add up5k timings
X-Git-Tag: working-ls180~1237^2~201
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c0853fc518bbbad77b819a5c916e438d0e33cb0;p=yosys.git

Add up5k timings
---

diff --git a/techlibs/ice40/up5k.box b/techlibs/ice40/up5k.box
new file mode 100644
index 000000000..94df1df8f
--- /dev/null
+++ b/techlibs/ice40/up5k.box
@@ -0,0 +1,13 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+
+# NB: Inputs/Outputs must be ordered alphabetically
+
+# Inputs: CI I0 I1
+# Outputs: CO
+SB_CARRY 1 1 3 1
+278 675 609
+
+# Inputs: I0 I1 I2 I3
+# Outputs: O
+SB_LUT4 2 1 4 1
+1285 1231 1205 874
diff --git a/techlibs/ice40/up5k.lut b/techlibs/ice40/up5k.lut
new file mode 100644
index 000000000..1e4fcadb6
--- /dev/null
+++ b/techlibs/ice40/up5k.lut
@@ -0,0 +1,6 @@
+# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
+#       I3  I2  I1  I0
+1   1   874
+2   1   874 1205
+3   1   874 1205 1231
+4   1   874 1205 1231 1285