From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Wed, 14 Mar 2012 11:19:42 +0000 (+0100)
Subject: fhdl: export log2_int
X-Git-Tag: 24jan2021_ls180~2099^2~968
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c0cc6292c440e19dab5594477452769ca37dd71;p=litex.git

fhdl: export log2_int
---

diff --git a/migen/bus/wishbone2asmi.py b/migen/bus/wishbone2asmi.py
index 23544d0d..178925a2 100644
--- a/migen/bus/wishbone2asmi.py
+++ b/migen/bus/wishbone2asmi.py
@@ -4,17 +4,6 @@ from migen.corelogic.fsm import FSM
 from migen.corelogic.misc import split, displacer, chooser
 from migen.corelogic.record import Record
 
-def _log2_int(n):
-	l = 1
-	r = 0
-	while l < n:
-		l *= 2
-		r += 1
-	if l == n:
-		return r
-	else:
-		raise ValueError("Not a power of 2")
-
 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
 class WB2ASMI:
 	def __init__(self, cachesize, asmiport):
@@ -37,9 +26,9 @@ class WB2ASMI:
 		
 		# Split address:
 		# TAG | LINE NUMBER | LINE OFFSET
-		offsetbits = _log2_int(adw//32)
+		offsetbits = log2_int(adw//32)
 		addressbits = aaw + offsetbits
-		linebits = _log2_int(self.cachesize) - offsetbits
+		linebits = log2_int(self.cachesize) - offsetbits
 		tagbits = aaw - linebits
 		adr_offset, adr_line, adr_tag = split(self.wishbone.adr, offsetbits, linebits, tagbits)
 		
diff --git a/migen/fhdl/structure.py b/migen/fhdl/structure.py
index 748ea059..89545c79 100644
--- a/migen/fhdl/structure.py
+++ b/migen/fhdl/structure.py
@@ -4,6 +4,17 @@ import re
 
 from migen.fhdl import tracer
 
+def log2_int(n):
+	l = 1
+	r = 0
+	while l < n:
+		l *= 2
+		r += 1
+	if l == n:
+		return r
+	else:
+		raise ValueError("Not a power of 2")
+
 def bits_for(n):
 	if isinstance(n, Constant):
 		return n.bv.width