From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 17 Apr 2019 04:05:44 +0000 (-0700)
Subject: Optimise
X-Git-Tag: working-ls180~1237^2~220
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c134980c4d0f5c1f961d50c9c1fe1752d966e48;p=yosys.git

Optimise
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index ce93ffb28..06496dbc3 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -585,18 +585,17 @@ struct XAigerWriter
 				if (holes_module && !holes_module->cell(stringf("\\u%d", box_id)))
 					holes_cell = holes_module->addCell(stringf("\\u%d", box_id), cell->type);
 				RTLIL::Wire *holes_wire;
-				int num_inputs = 0;
 				// NB: cell->connections_ already sorted from before
 				for (const auto &c : cell->connections()) {
+					log_assert(c.second.size() == 1);
 					if (cell->input(c.first)) {
 						box_inputs += c.second.size();
 						if (holes_cell) {
-							holes_wire = holes_module->wire(stringf("\\i%d", num_inputs));
+							holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
 							if (!holes_wire) {
-								holes_wire = holes_module->addWire(stringf("\\i%d", num_inputs));
+								holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
 								holes_wire->port_input = true;
 							}
-							++num_inputs;
 							holes_cell->setPort(c.first, holes_wire);
 						}
 					}