From: Florent Kermarrec Date: Sun, 2 Jun 2013 13:15:47 +0000 (+0200) Subject: simplify signals connexion X-Git-Tag: 24jan2021_ls180~2575^2~96 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c298f406cca361d7161cc50da952e484ad467cd;p=litex.git simplify signals connexion --- diff --git a/examples/de0_nano/top.py b/examples/de0_nano/top.py index 0e3ae09d..cc363f26 100644 --- a/examples/de0_nano/top.py +++ b/examples/de0_nano/top.py @@ -53,7 +53,7 @@ class SoC(Module): self.submodules.trigger = trigger.Trigger(trig_w, [self.term]) self.submodules.recorder = recorder.Recorder(dat_w, rec_size) - self.submodules.mila = mila.MiLa(MILA_ADDR, self.trigger, self.recorder) + self.submodules.mila = mila.MiLa(MILA_ADDR, self.trigger, self.recorder, trig_is_dat=True) # Uart2Csr self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200) @@ -94,13 +94,11 @@ class SoC(Module): # Mila # self.comb +=[ - self.mila.trig[0].eq(self.freqgen.o), - self.mila.trig[1].eq(self.eventgen_rising.o), - self.mila.trig[2].eq(self.eventgen_falling.o), - self.mila.trig[3:11].eq(self.cnt), - self.mila.dat[0].eq(self.freqgen.o), - self.mila.dat[1].eq(self.eventgen_rising.o), - self.mila.dat[2].eq(self.eventgen_falling.o), - self.mila.dat[3:11].eq(self.cnt), + self.mila.trig.eq(Cat( + self.freqgen.o, + self.eventgen_rising.o, + self.eventgen_falling.o, + self.cnt) + ) ] self.sync += self.cnt.eq(self.cnt+1) diff --git a/miscope/miio.py b/miscope/miio.py index db71d7bb..b2512cb5 100644 --- a/miscope/miio.py +++ b/miscope/miio.py @@ -3,6 +3,8 @@ from migen.bus import csr from migen.bank import csrgen from migen.bank.description import * +from miscope.tools.misc import * + class MiIo: # # Definition @@ -38,7 +40,7 @@ class MiIo: # Driver # def set(self, data): - self.interface.write(self.bank.get_base(), data) + self.interface.write(get_csr_base(self.bank), data) def get(self): - return self.interface.read(self.bank.get_base() + self.words) \ No newline at end of file + return self.interface.read(get_csr_base(self.bank) + self.words) \ No newline at end of file diff --git a/miscope/mila.py b/miscope/mila.py index 7286e4ee..341b135a 100644 --- a/miscope/mila.py +++ b/miscope/mila.py @@ -4,13 +4,15 @@ from migen.bank import description, csrgen from migen.bank.description import * from miscope import trigger, recorder +from miscope.tools.misc import * class MiLa: - def __init__(self, address, trigger, recorder, interface=None): + def __init__(self, address, trigger, recorder, interface=None, trig_is_dat=False): self.trigger = trigger self.recorder = recorder self.interface = interface + self.trig_is_dat = trig_is_dat self.stb = Signal(reset=1) self.trig = Signal(self.trigger.width) @@ -34,7 +36,13 @@ class MiLa: self.recorder.stb.eq(self.stb), self.trigger.trig.eq(self.trig), - self.recorder.dat.eq(self.dat), self.recorder.hit.eq(self.trigger.hit) ] + if self.trig_is_dat: + comb +=[ + self.recorder.dat.eq(self.trig), + ] + else: + self.recorder.dat.eq(self.dat), + return Fragment(comb) \ No newline at end of file diff --git a/miscope/recorder.py b/miscope/recorder.py index d0d5edc3..47771642 100644 --- a/miscope/recorder.py +++ b/miscope/recorder.py @@ -6,7 +6,7 @@ from migen.bank.description import * from migen.genlib.misc import optree from migen.genlib.fsm import * -from miscope.tools.misc import RisingEdge +from miscope.tools.misc import * class Storage: # @@ -291,34 +291,34 @@ class Recorder: # Driver # def reset(self): - self.interface.write(self.bank.get_base() + REC_RST_BASE, 1) - self.interface.write(self.bank.get_base() + REC_RST_BASE, 0) + self.interface.write(get_csr_base(self.bank) + REC_RST_BASE, 1) + self.interface.write(get_csr_base(self.bank) + REC_RST_BASE, 0) def enable_rle(self): - self.interface.write(self.bank.get_base() + REC_RLE_BASE, 1) + self.interface.write(get_csr_base(self.bank) + REC_RLE_BASE, 1) def disable_rle(self): - self.interface.write(self.bank.get_base() + REC_RLE_BASE, 0) + self.interface.write(get_csr_base(self.bank) + REC_RLE_BASE, 0) def arm(self): - self.interface.write(self.bank.get_base() + REC_ARM_BASE, 1) - self.interface.write(self.bank.get_base() + REC_ARM_BASE, 0) + self.interface.write(get_csr_base(self.bank) + REC_ARM_BASE, 1) + self.interface.write(get_csr_base(self.bank) + REC_ARM_BASE, 0) def is_done(self): - return self.interface.read(self.bank.get_base() + REC_DONE_BASE) == 1 + return self.interface.read(get_csr_base(self.bank) + REC_DONE_BASE) == 1 def set_size(self, dat): - self.interface.write_n(self.bank.get_base() + REC_SIZE_BASE, dat, 16) + self.interface.write_n(get_csr_base(self.bank) + REC_SIZE_BASE, dat, 16) def set_offset(self, dat): - self.interface.write_n(self.bank.get_base() + REC_OFFSET_BASE, dat, 16) + self.interface.write_n(get_csr_base(self.bank) + REC_OFFSET_BASE, dat, 16) def pull(self, size): r = [] for i in range(size): - self.interface.write(self.bank.get_base() + REC_READ_BASE, 1) - self.interface.write(self.bank.get_base() + REC_READ_BASE, 0) - r.append(self.interface.read_n(self.bank.get_base() + REC_READ_DATA_BASE, self.width)) + self.interface.write(get_csr_base(self.bank) + REC_READ_BASE, 1) + self.interface.write(get_csr_base(self.bank) + REC_READ_BASE, 0) + r.append(self.interface.read_n(get_csr_base(self.bank) + REC_READ_DATA_BASE, self.width)) if i%128 == 0: print(i) return r diff --git a/miscope/tools/misc.py b/miscope/tools/misc.py index 1067a5c4..5e780a7e 100644 --- a/miscope/tools/misc.py +++ b/miscope/tools/misc.py @@ -108,4 +108,16 @@ class PwrOnRst(Module): ] else: self.comb += self.rst.eq(0) - self._fragment += Fragment(sync={"sys_no_reset" : sync_no_reset}) \ No newline at end of file + self._fragment += Fragment(sync={"sys_no_reset" : sync_no_reset}) + +def get_csr_base(bank, name=None): + base = 0 + if name != None: + base = None + for i, c in enumerate(bank.simple_csrs): + if name in c.name: + if base == None: + base = i + elif base >= i: + base = i + return (bank.address<<9) + base \ No newline at end of file diff --git a/miscope/trigger.py b/miscope/trigger.py index 603f0c9c..61a9a8d3 100644 --- a/miscope/trigger.py +++ b/miscope/trigger.py @@ -5,6 +5,7 @@ from migen.bank import description, csrgen from migen.bank.description import * from migen.genlib.misc import optree +from miscope.tools.misc import * class RegParams: def __init__(self, name, base, width, nb): @@ -281,8 +282,8 @@ class Trigger: self.address = address self.bank = csrgen.Bank(self.regs, address=self.address) for port in self.ports: - port.reg_p.base = self.bank.get_base(port.reg_p.name) - self.sum.reg_p.base = self.bank.get_base(self.sum.reg_p.name) + port.reg_p.base = get_csr_base(self.bank, port.reg_p.name) + self.sum.reg_p.base = get_csr_base(self.bank, self.sum.reg_p.name) def set_interface(self, interface): self.interface = interface