From: Chung-Ju Wu Date: Thu, 5 Apr 2018 02:23:19 +0000 (+0000) Subject: [NDS32] The add and sub pattens should only accept si mode. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c36be57336c5d4c3b989e9be5bbe060a0deba12;p=gcc.git [NDS32] The add and sub pattens should only accept si mode. gcc/ * config/nds32/nds32.md (add3, sub3): Rename to ... (addsi3, subsi3): ... this. From-SVN: r259116 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index fe76138ad0b..da7eed24019 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2018-04-05 Chung-Ju Wu + + * config/nds32/nds32.md (add3, sub3): Rename to ... + (addsi3, subsi3): ... this. + 2018-04-05 Chung-Ju Wu * config/nds32/nds32.md (*sub_srli, *and_slli): Fine-tune predicator. diff --git a/gcc/config/nds32/nds32.md b/gcc/config/nds32/nds32.md index 0189bdf7b6c..95345ff7af8 100644 --- a/gcc/config/nds32/nds32.md +++ b/gcc/config/nds32/nds32.md @@ -320,10 +320,10 @@ ;; Arithmetic instructions. -(define_insn "add3" - [(set (match_operand:QIHISI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") - (plus:QIHISI (match_operand:QIHISI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") - (match_operand:QIHISI 2 "nds32_rimm15s_operand" " In05, In03, Iu05, Iu03, r, l, Is10, Iu06, Is15, r")))] +(define_insn "addsi3" + [(set (match_operand:SI 0 "register_operand" "= d, l, d, l, d, l, k, l, r, r") + (plus:SI (match_operand:SI 1 "register_operand" "% 0, l, 0, l, 0, l, 0, k, r, r") + (match_operand:SI 2 "nds32_rimm15s_operand" " In05,In03,Iu05,Iu03, r, l,Is10,IU06, Is15, r")))] "" { switch (which_alternative) @@ -363,10 +363,10 @@ (set_attr "length" " 2, 2, 2, 2, 2, 2, 2, 2, 4, 4") (set_attr "feature" " v1, v1, v1, v1, v1, v1, v2, v1, v1, v1")]) -(define_insn "sub3" - [(set (match_operand:QIHISI 0 "register_operand" "=d, l, r, r") - (minus:QIHISI (match_operand:QIHISI 1 "nds32_rimm15s_operand" " 0, l, Is15, r") - (match_operand:QIHISI 2 "register_operand" " r, l, r, r")))] +(define_insn "subsi3" + [(set (match_operand:SI 0 "register_operand" "=d, l, r, r") + (minus:SI (match_operand:SI 1 "nds32_rimm15s_operand" " 0, l, Is15, r") + (match_operand:SI 2 "register_operand" " r, l, r, r")))] "" "@ sub45\t%0, %2