From: Gabe Black Date: Thu, 9 Jul 2009 06:02:21 +0000 (-0700) Subject: Registers: Eliminate the ISA defined RegFile class. X-Git-Tag: Calvin_Submission~219^2~12 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c37d10624e0f9a9568f1eb1527832c55addba59;p=gem5.git Registers: Eliminate the ISA defined RegFile class. --- diff --git a/src/arch/alpha/miscregfile.hh b/src/arch/alpha/miscregfile.hh index 0d95e5a6d..b231ea855 100644 --- a/src/arch/alpha/miscregfile.hh +++ b/src/arch/alpha/miscregfile.hh @@ -57,7 +57,6 @@ enum MiscRegIndex class MiscRegFile { public: - friend class RegFile; typedef uint64_t InternalProcReg; protected: diff --git a/src/arch/alpha/regfile.cc b/src/arch/alpha/regfile.cc index 15df83859..8b226a9cf 100644 --- a/src/arch/alpha/regfile.cc +++ b/src/arch/alpha/regfile.cc @@ -52,22 +52,6 @@ const int reg_redir[NumIntRegs] = { /* 24 */ 24, 25, 26, 27, 28, 29, 30, 31 }; #endif -void -RegFile::serialize(EventManager *em, ostream &os) -{ -#if FULL_SYSTEM - SERIALIZE_SCALAR(intrflag); -#endif -} - -void -RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion) -{ -#if FULL_SYSTEM - UNSERIALIZE_SCALAR(intrflag); -#endif -} - void copyRegs(ThreadContext *src, ThreadContext *dest) { diff --git a/src/arch/alpha/regfile.hh b/src/arch/alpha/regfile.hh index 39c56e57a..e7374036f 100644 --- a/src/arch/alpha/regfile.hh +++ b/src/arch/alpha/regfile.hh @@ -46,22 +46,6 @@ namespace AlphaISA { // redirected register map, really only used for the full system case. extern const int reg_redir[NumIntRegs]; -class RegFile { - public: -#if FULL_SYSTEM - int intrflag; // interrupt flag -#endif // FULL_SYSTEM - - void - clear() - { - } - - void serialize(EventManager *em, std::ostream &os); - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion); -}; - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index b79c09174..3d882c97f 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -433,7 +433,6 @@ void InterruptFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(Arm,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; @@ -469,7 +468,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(Arm,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; HandlerBase= vect() + tc->readMiscRegNoEffect(ArmISA::EBase); // Offset 0x180 - General Exception Vector diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh index c2b2f39d7..e89826956 100644 --- a/src/arch/arm/regfile/misc_regfile.hh +++ b/src/arch/arm/regfile/misc_regfile.hh @@ -84,8 +84,6 @@ namespace ArmISA assert(misc_reg < NumMiscRegs); miscRegFile[misc_reg] = val; } - - friend class RegFile; }; } // namespace ArmISA diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index cd2d4ee2c..c7f23c704 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -93,20 +93,6 @@ namespace ArmISA r14_abt }; - class RegFile - { - public: - - void clear() - {} - - void serialize(EventManager *em, std::ostream &os) - {} - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) - {} - }; - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc index 63884e837..347d041a3 100644 --- a/src/arch/mips/faults.cc +++ b/src/arch/mips/faults.cc @@ -435,7 +435,6 @@ void InterruptFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(MipsPRA,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; @@ -471,7 +470,6 @@ void ReservedInstructionFault::invoke(ThreadContext *tc) { #if FULL_SYSTEM DPRINTF(MipsPRA,"%s encountered.\n", name()); - //RegFile *Reg = tc->getRegFilePtr(); // Get pointer to the register fil setExceptionState(tc,0x0A); Addr HandlerBase; HandlerBase= vect() + tc->readMiscRegNoEffect(MipsISA::EBase); // Offset 0x180 - General Exception Vector diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh index 633ea7efb..ab233abde 100644 --- a/src/arch/mips/regfile/misc_regfile.hh +++ b/src/arch/mips/regfile/misc_regfile.hh @@ -48,9 +48,6 @@ namespace MipsISA { class MiscRegFile { public: - // Give RegFile object, private access - friend class RegFile; - // The MIPS name for this file is CP0 or Coprocessor 0 typedef MiscRegFile CP0; diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh index 71775edc4..be67894bf 100644 --- a/src/arch/mips/regfile/regfile.hh +++ b/src/arch/mips/regfile/regfile.hh @@ -92,27 +92,6 @@ namespace MipsISA //TotalArchRegs = NumIntArchRegs * ShadowSets const int TotalArchRegs = NumIntArchRegs; - - class RegFile { - public: - void clear() - {} - void reset(std::string core_name, ThreadID num_threads, - unsigned num_vpes, BaseCPU *_cpu) - {} - - void setShadowSet(int css) - {} - - public: - void serialize(EventManager *em, std::ostream &os) - {} - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) - {} - - }; - } // namespace MipsISA #endif diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh index 00dadcf3d..407602f90 100644 --- a/src/arch/sparc/isa_traits.hh +++ b/src/arch/sparc/isa_traits.hh @@ -44,8 +44,6 @@ namespace BigEndianGuest {} namespace SparcISA { - class RegFile; - const int MachineBytes = 8; //This makes sure the big endian versions of certain functions are used. diff --git a/src/arch/sparc/regfile.hh b/src/arch/sparc/regfile.hh index b0c2aabbd..28885271f 100644 --- a/src/arch/sparc/regfile.hh +++ b/src/arch/sparc/regfile.hh @@ -47,20 +47,6 @@ namespace SparcISA const int NumIntArchRegs = 32; const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; - class RegFile - { - public: - - void clear() - {} - - void serialize(EventManager *em, std::ostream &os) - {} - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) - {} - }; - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/arch/x86/regfile.hh b/src/arch/x86/regfile.hh index 6c0dc757e..fd9d6d546 100644 --- a/src/arch/x86/regfile.hh +++ b/src/arch/x86/regfile.hh @@ -84,19 +84,6 @@ namespace X86ISA NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs; const int NumFloatArchRegs = NumFloatRegs + 8; - class RegFile - { - public: - void clear() - {} - - void serialize(EventManager *em, std::ostream &os) - {} - void unserialize(EventManager *em, Checkpoint *cp, - const std::string §ion) - {} - }; - void copyRegs(ThreadContext *src, ThreadContext *dest); void copyMiscRegs(ThreadContext *src, ThreadContext *dest); diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh index 31010a01f..595a38ecc 100644 --- a/src/cpu/inorder/cpu.hh +++ b/src/cpu/inorder/cpu.hh @@ -77,7 +77,6 @@ class InOrderCPU : public BaseCPU typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; typedef TheISA::FloatRegBits FloatRegBits; - typedef TheISA::RegFile RegFile; typedef TheISA::MiscReg MiscReg; //DynInstPtr TypeDefs diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc index 2edaf8f55..dde63d7d9 100644 --- a/src/cpu/simple_thread.cc +++ b/src/cpu/simple_thread.cc @@ -110,7 +110,6 @@ SimpleThread::SimpleThread() #endif { tc = new ProxyThreadContext(this); - regs.clear(); } SimpleThread::~SimpleThread() @@ -191,7 +190,6 @@ void SimpleThread::serialize(ostream &os) { ThreadState::serialize(os); - regs.serialize(cpu, os); SERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); SERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); SERIALIZE_SCALAR(microPC); @@ -207,7 +205,6 @@ void SimpleThread::unserialize(Checkpoint *cp, const std::string §ion) { ThreadState::unserialize(cp, section); - regs.unserialize(cpu, cp, section); UNSERIALIZE_ARRAY(floatRegs.i, TheISA::NumFloatRegs); UNSERIALIZE_ARRAY(intRegs, TheISA::NumIntRegs); UNSERIALIZE_SCALAR(microPC); diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh index 31e69bafe..90502fe9f 100644 --- a/src/cpu/simple_thread.hh +++ b/src/cpu/simple_thread.hh @@ -90,7 +90,6 @@ class TranslatingPort; class SimpleThread : public ThreadState { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; typedef TheISA::MiscReg MiscReg; typedef TheISA::FloatReg FloatReg; @@ -99,7 +98,6 @@ class SimpleThread : public ThreadState typedef ThreadContext::Status Status; protected: - RegFile regs; // correct-path register context union { FloatReg f[TheISA::NumFloatRegs]; FloatRegBits i[TheISA::NumFloatRegs]; @@ -253,7 +251,6 @@ class SimpleThread : public ThreadState void clearArchRegs() { - regs.clear(); microPC = 0; nextMicroPC = 1; PC = nextPC = nextNPC = 0; diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 49776858d..98d244994 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -79,7 +79,6 @@ namespace TheISA { class ThreadContext { protected: - typedef TheISA::RegFile RegFile; typedef TheISA::MachInst MachInst; typedef TheISA::IntReg IntReg; typedef TheISA::FloatReg FloatReg; diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh index 8624b44da..98908766b 100644 --- a/src/kern/tru64/tru64.hh +++ b/src/kern/tru64/tru64.hh @@ -496,7 +496,6 @@ class Tru64 : public OperatingSystem { using namespace TheISA; - using TheISA::RegFile; TypedBufferArg sc(process->getSyscallArg(tc, 0)); sc.copyIn(tc->getMemPort());