From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 25 Jun 2020 14:54:10 +0000 (+0100)
Subject: add regfile link
X-Git-Tag: convert-csv-opcode-to-binary~2414
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c3dcec55564a933b73762125dbe9aac6943c8f4;p=libreriscv.git

add regfile link
---

diff --git a/3d_gpu/architecture/regfile.mdwn b/3d_gpu/architecture/regfile.mdwn
index 551d54a16..4ea2234d9 100644
--- a/3d_gpu/architecture/regfile.mdwn
+++ b/3d_gpu/architecture/regfile.mdwn
@@ -1,6 +1,10 @@
 # Register Files
 
-A minimum of 3 register files are required for POWER:
+Discussion:
+
+* <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2020-June/008368.html>
+
+A minimum of 4 register files are required for POWER:
 
 * Floating-point
 * Integer