From: Andrea Corallo <andrea.corallo@arm.com>
Date: Tue, 8 Jun 2021 17:03:29 +0000 (+0200)
Subject: PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c43020d83f9f3529e71fcd19f3f78e0abcbe5ed;p=binutils-gdb.git

PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extension

gas/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* config/tc-arm.c (T16_32_TAB): Add '_pacg'.
	(do_t_pacbti_pacg): New function.
	(insns): Define 'pacg' insn.
	* testsuite/gas/arm/armv8_1-m-pacbti.d: Add 'pacg' test.
	* testsuite/gas/arm/armv8_1-m-pacbti.s: Likewise.

opcodes/
2021-06-11  Andrea Corallo  <andrea.corallo@arm.com>

	* arm-dis.c (thumb32_opcodes): Add 'pacg'.
---

diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c
index cd65b25601e..40e9d2e02f2 100644
--- a/gas/config/tc-arm.c
+++ b/gas/config/tc-arm.c
@@ -11513,6 +11513,7 @@ encode_thumb32_addr_mode (int i, bool is_t, bool is_d)
   X(_orrs,  4300, ea500000),			\
   X(_pac,   0000, f3af801d),			\
   X(_pacbti, 0000, f3af800d),			\
+  X(_pacg,  0000, fb60f000),			\
   X(_pop,   bc00, e8bd0000), /* ldmia sp!,... */	\
   X(_push,  b400, e92d0000), /* stmdb sp!,... */	\
   X(_rev,   ba00, fa90f080),			\
@@ -22357,6 +22358,18 @@ do_t_pacbti_nonop (void)
   inst.instruction |= inst.operands[2].reg;
 }
 
+static void
+do_t_pacbti_pacg (void)
+{
+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, pacbti_ext),
+	      _(BAD_PACBTI));
+
+  inst.instruction = THUMB_OP32 (inst.instruction);
+  inst.instruction |= inst.operands[0].reg << 8;
+  inst.instruction |= inst.operands[1].reg << 16;
+  inst.instruction |= inst.operands[2].reg;
+}
+
 
 /* Overall per-instruction processing.	*/
 
@@ -26351,6 +26364,7 @@ static const struct asm_opcode insns[] =
  toU("bxaut", _bxaut, 3, (RR, RR, RR), t_pacbti_nonop),
  toU("pac",   _pac,   3, (R12, LR, SP), t_pacbti),
  toU("pacbti", _pacbti, 3, (R12, LR, SP), t_pacbti),
+ toU("pacg",   _pacg,   3, (RR, RR, RR), t_pacbti_pacg),
  toU("cinc",  _cinc,  3, (RRnpcsp, RR_ZR, COND),	t_cond),
  toU("cinv",  _cinv,  3, (RRnpcsp, RR_ZR, COND),	t_cond),
  toU("cneg",  _cneg,  3, (RRnpcsp, RR_ZR, COND),	t_cond),
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
index 6ddf218c9f9..2e7082216ce 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.d
@@ -12,4 +12,5 @@ Disassembly of section .text:
 0[0-9a-f]+ <[^>]+> f3af 801d 	pac	r12, lr, sp
 0[0-9a-f]+ <[^>]+> fb54 3f15 	bxaut	r3, r4, r5
 0[0-9a-f]+ <[^>]+> fb54 3f05 	autg	r3, r4, r5
+0[0-9a-f]+ <[^>]+> fb64 f305 	pacg	r3, r4, r5
 #...
diff --git a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
index eccd5797ed7..8d3a4a44c1c 100644
--- a/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
+++ b/gas/testsuite/gas/arm/armv8_1-m-pacbti.s
@@ -8,3 +8,4 @@
 	pac	r12, lr, sp
 	bxaut	r3, r4, r5
 	autg	r3, r4, r5
+	pacg	r3, r4, r5
diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index d54cfa8fe84..faabd42b5b3 100644
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -4666,6 +4666,8 @@ static const struct opcode32 thumb32_opcodes[] =
    0xf3af801d, 0xffffffff, "pac\tr12, lr, sp"},
   {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN),
    0xf3af800d, 0xffffffff, "pacbti\tr12, lr, sp"},
+  {ARM_FEATURE_CORE_HIGH_HIGH (ARM_EXT3_PACBTI),
+   0xfb60f000, 0xfff0f0f0, "pacg%c\t%8-11r, %16-19r, %0-3r"},
 
   /* Armv8.1-M Mainline and Armv8.1-M Mainline Security Extensions
      instructions.  */