From: Richard Earnshaw <Richard.Earnshaw@arm.com>
Date: Thu, 20 Nov 2014 15:28:52 +0000 (+0000)
Subject: [AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c47e525893b06db772d8b1c043233a173101c8c;p=binutils-gdb.git

[AArch64] Fix mis-detection of unpredictable load/store operations with FP regs.

	* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
	registers are in the GP register set.  Adjust warnings.  Use correct
	field member for address register.
	* testsuite/gas/aarch64/diagnostic.l: Update.
---

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 8341ee415a2..97e5a9ef9b6 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2014-11-20  Richard Earnshaw  <rearnsha@arm.com>
+
+	* config/tc-aarch64.c (warn_unpredictable_ldst): Check that transfer
+	registers are in the GP register set.  Adjust warnings.  Use correct
+	field member for address register.
+	* testsuite/gas/aarch64/diagnostic.l: Update.
+
 2014-11-19  Ryan Mansfield  <rmansfield@qnx.com>
 
 	* config/tc-aarch64.c (md_assemble): Call warn_unpredictable_ldst.
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 41378f5deba..c8824e56777 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -5490,7 +5490,7 @@ programmer_friendly_fixup (aarch64_instruction *instr)
   return TRUE;
 }
 
-/* Check for loads and stores that will cause unpredictable behavior */
+/* Check for loads and stores that will cause unpredictable behavior.  */
 
 static void
 warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
@@ -5504,17 +5504,24 @@ warn_unpredictable_ldst (aarch64_instruction *instr, char *str)
     case ldst_imm9:
     case ldst_unscaled:
     case ldst_unpriv:
-      if (opnds[0].reg.regno == opnds[1].reg.regno
+      /* Loading/storing the base register is unpredictable if writeback.  */
+      if ((aarch64_get_operand_class (opnds[0].type)
+	   == AARCH64_OPND_CLASS_INT_REG)
+	  && opnds[0].reg.regno == opnds[1].addr.base_regno
 	  && opnds[1].addr.writeback)
-	as_warn (_("unpredictable register after writeback -- `%s'"), str);
+	as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
       break;
     case ldstpair_off:
     case ldstnapair_offs:
     case ldstpair_indexed:
-      if ((opnds[0].reg.regno == opnds[2].reg.regno
-	    || opnds[1].reg.regno == opnds[2].reg.regno)
+      /* Loading/storing the base register is unpredictable if writeback.  */
+      if ((aarch64_get_operand_class (opnds[0].type)
+	   == AARCH64_OPND_CLASS_INT_REG)
+	  && (opnds[0].reg.regno == opnds[2].addr.base_regno
+	    || opnds[1].reg.regno == opnds[2].addr.base_regno)
 	  && opnds[2].addr.writeback)
-	    as_warn (_("unpredictable register after writeback -- `%s'"), str);
+	    as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
+      /* Load operations must load different registers.  */
       if ((opcode->opcode & (1 << 22))
 	  && opnds[0].reg.regno == opnds[1].reg.regno)
 	    as_warn (_("unpredictable load of register pair -- `%s'"), str);
diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index d5fdba8c17d..61ce5d26946 100644
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -109,8 +109,8 @@
 [^:]*:116: Warning: unpredictable load of register pair -- `ldp d0,d0,\[sp\]'
 [^:]*:117: Warning: unpredictable load of register pair -- `ldp x0,x0,\[sp\],#16'
 [^:]*:118: Warning: unpredictable load of register pair -- `ldnp x0,x0,\[sp\]'
-[^:]*:121: Warning: unpredictable register after writeback -- `ldr x0,\[x0,#8\]!'
-[^:]*:122: Warning: unpredictable register after writeback -- `str x0,\[x0,#8\]!'
-[^:]*:123: Warning: unpredictable register after writeback -- `str x1,\[x1\],#8'
-[^:]*:124: Warning: unpredictable register after writeback -- `stp x0,x1,\[x0,#16\]!'
-[^:]*:125: Warning: unpredictable register after writeback -- `ldp x0,x1,\[x1\],#16'
+[^:]*:121: Warning: unpredictable transfer with writeback -- `ldr x0,\[x0,#8\]!'
+[^:]*:122: Warning: unpredictable transfer with writeback -- `str x0,\[x0,#8\]!'
+[^:]*:123: Warning: unpredictable transfer with writeback -- `str x1,\[x1\],#8'
+[^:]*:124: Warning: unpredictable transfer with writeback -- `stp x0,x1,\[x0,#16\]!'
+[^:]*:125: Warning: unpredictable transfer with writeback -- `ldp x0,x1,\[x1\],#16'