From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 10 Aug 2021 11:42:41 +0000 (+0100)
Subject: corrections to SVP64 Branch RM Mode decoding
X-Git-Tag: xlen-bcd~149
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c4c4b3bac8ce55414223496116d250b59459ebf;p=openpower-isa.git

corrections to SVP64 Branch RM Mode decoding
---

diff --git a/src/openpower/consts.py b/src/openpower/consts.py
index f55eedc3..08b9a611 100644
--- a/src/openpower/consts.py
+++ b/src/openpower/consts.py
@@ -225,8 +225,10 @@ class SVP64MODEb:
     LDST_SHIFT = 2 # set =1 for shift mode
     # when predicate not set: 0=ignore/skip 1=zero
     DZ = 3  # for destination
-    BC_SNZ = 3  # for branch-conditional mode
     SZ = 4  # for source
+    # for branch-conditional
+    BC_SNZ = 3  # for branch-conditional mode
+    BC_VLI = 2  # for VL include/exclude on VLSET mode
     # reduce mode
     REDUCE = 2  # 0=normal predication 1=reduce mode
     PARALLEL = 3 # 1=parallel reduce, 0=scalar reduce
diff --git a/src/openpower/decoder/power_svp64_rm.py b/src/openpower/decoder/power_svp64_rm.py
index 654b9b5b..9af4c1fd 100644
--- a/src/openpower/decoder/power_svp64_rm.py
+++ b/src/openpower/decoder/power_svp64_rm.py
@@ -107,6 +107,7 @@ class SVP64RMModeDecode(Elaboratable):
         self.bc_vlset = Signal(SVP64BCVLSETMode) # Branch-Conditional VLSET
         self.bc_step = Signal(SVP64BCStep)   # Branch-Conditional svstep mode
         self.bc_pred = Signal(SVP64BCPredMode) # BC predicate mode
+        self.bc_vsb = Signal()                 # BC VLSET-branch (like BO[1])
         self.bc_gate = Signal(SVP64BCGate)     # BC ALL or ANY gate
         self.bc_lru  = Signal()                # BC Link Register Update
 
@@ -148,14 +149,16 @@ class SVP64RMModeDecode(Elaboratable):
                     comb += self.bc_step.eq(SVP64BCStep.STEP)
             # VLSET mode
             with m.If(mode2[1]):
-                with m.If(self.rm_in.ewsrc[1]):
-                    comb += self.bc_step.eq(SVP64BCVLSETMode.VL_INCL)
+                with m.If(mode[SVP64MODE.BC_VLI]):
+                    comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_INCL)
                 with m.Else():
-                    comb += self.bc_step.eq(SVP64BCVLSETMode.VL_EXCL)
+                    comb += self.bc_vlset.eq(SVP64BCVLSETMode.VL_EXCL)
             # BC Mode ALL or ANY (Great-Big-AND-gate or Great-Big-OR-gate)
             comb += self.bc_gate.eq(self.rm_in.elwidth[0])
             # Link-Register Update
             comb += self.bc_lru.eq(self.rm_in.elwidth[1])
+            comb += self.bc_vsb.eq(self.rm_in.ewsrc[1])
+
         with m.Else():
             # combined arith / ldst decoding due to similarity
             with m.Switch(mode2):