From: lkcl <lkcl@web>
Date: Sun, 11 Jul 2021 23:00:52 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~628
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c7d0d1a49dce891328da3339f5e4537e95637d0;p=libreriscv.git

---

diff --git a/openpower/sv/setvl.mdwn b/openpower/sv/setvl.mdwn
index 4c1aa1159..3bd01a05b 100644
--- a/openpower/sv/setvl.mdwn
+++ b/openpower/sv/setvl.mdwn
@@ -72,12 +72,12 @@ Form: SVL-Form (see [[isatables/fields.text]])
 
 | 0.5|6.10|11.15|16..21|22| 23...25  | 26.30 |31|  name   |
 | -- | -- | --- | ---- |--| -------- | ----- |--| ------- |
-|OPCD| RT | RA  | SVi  |/ | vm vs ms | 11110 |Rc| setvl   |
+|OPCD| RT | RA  | SVi  |/ | ms vs vf | 11110 |Rc| setvl   |
 
 Note that the immediate (`SVi`) spans 7 bits (16 to 22)
 
-`ms` - bit 25 - allows for setting of MVL.  `vs` - bit 24 - allows for
-setting of VL.  `vm` - bit 23 - sets "Vertical Mode" which is
+`ms` - bit 23 - allows for setting of MVL.  `vs` - bit 24 - allows for
+setting of VL.  `vf` - bit 23 - sets "Vertical First Mode" which is
 stored in `MSR` bit 6 (**TODO: needs approval**)
 
 Note that in immediate setting mode VL and MVL start from **one**