From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 22 Aug 2019 02:18:27 +0000 (-0700)
Subject: Revert "Trim shiftx_width when upper bits are 1'bx"
X-Git-Tag: working-ls180~1085^2~70
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c8344363f6405d1d6e21868b10b6dc9e02148a4;p=yosys.git

Revert "Trim shiftx_width when upper bits are 1'bx"

This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb.
---

diff --git a/passes/pmgen/xilinx_srl.pmg b/passes/pmgen/xilinx_srl.pmg
index d3ba0109f..3f4efebe9 100644
--- a/passes/pmgen/xilinx_srl.pmg
+++ b/passes/pmgen/xilinx_srl.pmg
@@ -164,11 +164,6 @@ endmatch
 
 code shiftx_width
 	shiftx_width = param(shiftx, \A_WIDTH).as_int();
-	while (shiftx_width > 1) {
-		if (port(shiftx, \A)[shiftx_width-1] != State::Sx)
-			break;
-		--shiftx_width;
-	}
 endcode
 
 match first
@@ -182,7 +177,7 @@ code
 	chain.push_back(first);
 	subpattern(tail);
 finally
-	if (GetSize(chain) == shiftx_width)
+	if (GetSize(chain) == param(shiftx, \A_WIDTH).as_int())
 		accept;
 	chain.clear();
 endcode