From: Eric Anholt Date: Mon, 4 Feb 2013 18:00:10 +0000 (-0800) Subject: intel: Make intel_miptree_get_tile_offsets return a page offset. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c85e1cf554803e61bfb30f2a8683422a3ead0e4;p=mesa.git intel: Make intel_miptree_get_tile_offsets return a page offset. Right now, the callers in i965 don't expect a nonzero page offset to actually occur (since that's being handled elsewhere), but it seems like a trap to leave it this way. Reviewed-and-tested-by: Ian Romanick Acked-by: Paul Berry --- diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index bbe8579c553..2022159617e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -986,6 +986,8 @@ brw_update_texture_surface(struct gl_context *ctx, BRW_SURFACE_FORMAT_SHIFT)); surf[1] = intelObj->mt->region->bo->offset + intelObj->mt->offset; /* reloc */ + surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, + &tile_x, &tile_y); surf[2] = ((intelObj->_MaxLevel - tObj->BaseLevel) << BRW_SURFACE_LOD_SHIFT | (width - 1) << BRW_SURFACE_WIDTH_SHIFT | @@ -998,8 +1000,6 @@ brw_update_texture_surface(struct gl_context *ctx, surf[4] = brw_get_surface_num_multisamples(intelObj->mt->num_samples); - intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, - &tile_x, &tile_y); assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. @@ -1014,7 +1014,7 @@ brw_update_texture_surface(struct gl_context *ctx, drm_intel_bo_emit_reloc(brw->intel.batch.bo, binding_table[surf_index] + 4, intelObj->mt->region->bo, - intelObj->mt->offset, + surf[1] - intelObj->mt->region->bo->offset, I915_GEM_DOMAIN_SAMPLER, 0); } diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 435f9dc0041..c23a8bef88a 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -331,6 +331,8 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[0] |= GEN7_SURFACE_ARYSPC_LOD0; surf[1] = mt->region->bo->offset + mt->offset; /* reloc */ + surf[1] += intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, + &tile_x, &tile_y); surf[2] = SET_FIELD(width - 1, GEN7_SURFACE_WIDTH) | SET_FIELD(height - 1, GEN7_SURFACE_HEIGHT); @@ -339,8 +341,6 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[4] = gen7_surface_msaa_bits(mt->num_samples, mt->msaa_layout); - intel_miptree_get_tile_offsets(intelObj->mt, firstImage->Level, 0, - &tile_x, &tile_y); assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); /* Note that the low bits of these fields are missing, so * there's the possibility of getting in trouble. @@ -372,7 +372,8 @@ gen7_update_texture_surface(struct gl_context *ctx, /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, binding_table[surf_index] + 4, - intelObj->mt->region->bo, intelObj->mt->offset, + intelObj->mt->region->bo, + surf[1] - intelObj->mt->region->bo->offset, I915_GEM_DOMAIN_SAMPLER, 0); gen7_check_surface_setup(surf, false /* is_render_target */); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index d967b192e5e..02787999e84 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -777,19 +777,34 @@ intel_miptree_get_image_offset(struct intel_mipmap_tree *mt, *y = mt->level[level].slice[slice].y_offset; } -void +/** + * Rendering with tiled buffers requires that the base address of the buffer + * be aligned to a page boundary. For renderbuffers, and sometimes with + * textures, we may want the surface to point at a texture image level that + * isn't at a page boundary. + * + * This function returns an appropriately-aligned base offset + * according to the tiling restrictions, plus any required x/y offset + * from there. + */ +uint32_t intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt, GLuint level, GLuint slice, uint32_t *tile_x, uint32_t *tile_y) { struct intel_region *region = mt->region; + uint32_t x, y; uint32_t mask_x, mask_y; intel_region_get_tile_masks(region, &mask_x, &mask_y, false); + intel_miptree_get_image_offset(mt, level, slice, &x, &y); + + *tile_x = x & mask_x; + *tile_y = y & mask_y; - *tile_x = mt->level[level].slice[slice].x_offset & mask_x; - *tile_y = mt->level[level].slice[slice].y_offset & mask_y; + return intel_region_get_aligned_offset(region, x & ~mask_x, y & ~mask_y, + false); } static void diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h index b7376e03055..543182a0718 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h @@ -475,7 +475,7 @@ void intel_miptree_get_dimensions_for_image(struct gl_texture_image *image, int *width, int *height, int *depth); -void +uint32_t intel_miptree_get_tile_offsets(struct intel_mipmap_tree *mt, GLuint level, GLuint slice, uint32_t *tile_x,