From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 1 May 2022 10:45:58 +0000 (+0100)
Subject: cleanup on nextpnr-xilinx setup
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c88a0724d02528ddfcc263c4bb14c0186b3ca81;p=nmigen.git

cleanup on nextpnr-xilinx setup
* use rtlil instead of verilog (top.il not top.v)
* similar to nextpnr-ecp5 write out a top.ys file
* add top.tim and top.rpt outputting into build and set "quiet"
---

diff --git a/nmigen/vendor/xilinx.py b/nmigen/vendor/xilinx.py
index c72d728..79bb367 100644
--- a/nmigen/vendor/xilinx.py
+++ b/nmigen/vendor/xilinx.py
@@ -448,16 +448,40 @@ class XilinxPlatform(TemplatedPlatform):
         "fasm2frames",
         "xc7frames2bit"
     ]
+    # see explanation of yosys scratchpad command:
+    # https://github.com/gatecat/nextpnr-xilinx/issues/22#issuecomment-706710984
+    # also -nocarry option is needed due to P&R bugs when the carry-chains
+    # go beyond 23-25 CARRY4 blocks in length (appx 92-96 bit add/sub/cmp)
     _yosys_nextpnr_file_templates = {
         **TemplatedPlatform.build_script_templates,
-        "{{name}}.v": r"""
-            /* {{autogenerated}} */
-            {{emit_verilog()}}
+        "{{name}}.il": r"""
+            # {{autogenerated}}
+            {{emit_rtlil()}}
         """,
         "{{name}}.debug.v": r"""
             /* {{autogenerated}} */
             {{emit_debug_verilog()}}
         """,
+        "{{name}}.ys": r"""
+            # {{autogenerated}}
+            {% for file in platform.iter_files(".v") -%}
+                read_verilog {{get_override("read_verilog_opts")|options}} {{file}}
+            {% endfor %}
+            {% for file in platform.iter_files(".sv") -%}
+                read_verilog -sv {{get_override("read_verilog_opts")|options}} {{file}}
+            {% endfor %}
+            {% for file in platform.iter_files(".il") -%}
+                read_ilang {{file}}
+            {% endfor %}
+            read_ilang {{name}}.il
+            delete w:$verilog_initial_trigger
+            {{get_override("script_after_read")|default("# (script_after_read placeholder)")}}
+            scratchpad -set xilinx_dsp.multonly 1
+            synth_xilinx -flatten -nocarry -nobram -arch xc7 -top {{name}}
+            {{get_override("script_after_synth")|default("# (script_after_synth placeholder)")}}
+            write_json {{name}}.json
+        """,
+
         "{{name}}.xdc": r"""
             # {{autogenerated}}
             {% for port_name, pin_name, attrs in platform.iter_port_constraints_bits() -%}
@@ -468,10 +492,6 @@ class XilinxPlatform(TemplatedPlatform):
             {% endfor %}
         """,
     }
-    # see explanation of yosys scratchpad command:
-    # https://github.com/gatecat/nextpnr-xilinx/issues/22#issuecomment-706710984
-    # also -nocarry option is needed due to P&R bugs when the carry-chains
-    # go beyond 23-25 CARRY4 blocks in length (appx 92-96 bit add/sub/cmp)
     _yosys_nextpnr_command_templates = [
         r"""
         DB_DIR={{get_override("nextpnr_dir")|default("/usr/local/nextpnr-xilinx")}}/database
@@ -484,10 +504,15 @@ class XilinxPlatform(TemplatedPlatform):
         """,
         r"""
         {{invoke_tool("yosys")}}
-            -p "scratchpad -set xilinx_dsp.multonly 1; synth_xilinx -flatten -nocarry -nobram -arch xc7 -top {{name}}; write_json {{name}}.json" {% for file in platform.iter_files(".v", ".sv", ".vhd", ".vhdl") -%} {{file}} {% endfor %} {{name}}.v
+            {{quiet("-q")}}
+            {{get_override("yosys_opts")|options}}
+            -l {{name}}.rpt
+            {{name}}.ys
         """,
         r"""
         {{invoke_tool("nextpnr-xilinx")}}
+            {{quiet("--quiet")}}
+            --log {{name}}.tim
             --chipdb $CHIPDB_DIR/{{platform._yosys_nextpnr_device.get(platform.device, platform.device)}}.bin
             --xdc {{name}}.xdc
             --json {{name}}.json