From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Thu, 9 Sep 2010 22:41:59 +0000 (-0700)
Subject: Merge branch 'master' of /project/eecs/parlab/git/projects/riscv
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c88aa157be7696eac03b9fb1e36d19ccc96f5dc;p=riscv-isa-sim.git

Merge branch 'master' of /project/eecs/parlab/git/projects/riscv

Conflicts:
	sim/riscv/insns/mtpcr.h
	sim/riscv/processor.cc
---

5c88aa157be7696eac03b9fb1e36d19ccc96f5dc
diff --cc riscv/insns/mtpcr.h
index d9b47f0,5c7289e..79e28bf
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@@ -20,7 -15,8 +20,8 @@@ switch(insn.rtype.rb
      break;
  
    case 16:
 -    tohost = val;
 -    sim->set_tohost(tohost);
++    tohost = RA;
 +    sim->set_tohost(RA);
      break;
  
    case 24:
diff --cc riscv/processor.cc
index e04f498,e336aa1..271afbf
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@@ -21,10 -21,9 +21,12 @@@ processor_t::processor_t(sim_t* _sim, c
    tid = 0;
    pcr_k0 = 0;
    pcr_k1 = 0;
+   tohost = 0;
+   fromhost = 0;
 -  set_sr(SR_S | (support_64bit ? SR_KX : 0));
 +  count = 0;
 +  compare = 0;
 +  interrupts_pending = 0;
 +  set_sr(SR_S | (support_64bit ? SR_SX : 0));
    set_fsr(0);
  
    memset(counters,0,sizeof(counters));