From: lkcl <lkcl@web>
Date: Sun, 19 Jun 2022 19:47:33 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c915520ac12dc2e4bc16d6aa517ed0a61fef7ca;p=libreriscv.git

---

diff --git a/openpower/sv/av_opcodes.mdwn b/openpower/sv/av_opcodes.mdwn
index 51317dd8c..033a9147c 100644
--- a/openpower/sv/av_opcodes.mdwn
+++ b/openpower/sv/av_opcodes.mdwn
@@ -77,7 +77,10 @@ signed and unsigned, these are N-to-M (N=64/32/16, M=32/16/8) chop/clamp/sign/ze
 
 The other direction, vec_unpack widening ops, may need some way to tell whether to sign-extend or zero-extend.
 
-*scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest elwidth override provide the pack/unpack*
+*scalar extsw/b/h gives one set, mv gives another.  src elwidth override and dest elwidth override provide the pack/unpack*.
+
+implemented by [[sv/mv.vec]] RM Pack/Unpack mode as long as these instructions
+have that RM Mode.
  
 ## vavgs\* (vec_avg)