From: Lisa Hsu <hsul@eecs.umich.edu>
Date: Thu, 11 Jan 2007 14:48:15 +0000 (-0500)
Subject: Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
X-Git-Tag: m5_2.0_beta3~224^2~12
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5c9cbdbb4597a3ba6908a41c1dc459c25626e514;p=gem5.git

Merge zed.eecs.umich.edu:/z/hsul/work/sparc/ali.m5
into  zed.eecs.umich.edu:/z/hsul/work/sparc/m5

src/arch/sparc/ua2005.cc:
    hand merge between ali and me.

--HG--
extra : convert_revision : 810d63fb484ab26fc30f8130ef32390ba149b267
---

5c9cbdbb4597a3ba6908a41c1dc459c25626e514
diff --cc src/arch/sparc/ua2005.cc
index 128402fdd,4249bb05f..b8a891c6d
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@@ -44,8 -46,9 +44,10 @@@ MiscRegFile::setFSRegWithEffect(int mis
        case MISCREG_SOFTINT:
          // Check if we are going to interrupt because of something
          setReg(miscReg, val);
-         tc->getCpuPtr()->post_interrupt(soft_interrupt);
-         warn("Writing to softint not really supported, writing: %#x\n", val);
+         tc->getCpuPtr()->checkInterrupts = true;
++        tc->getCpuPtr()->post_interrupt(hstick_match);
+         if (val != 0x10000 && val != 0)
+             warn("Writing to softint not really supported, writing: %#x\n", val);
          break;
  
        case MISCREG_SOFTINT_CLR: