From: Doug Rupp <rupp@adacore.com>
Date: Wed, 16 Sep 2020 15:05:10 +0000 (-0700)
Subject: [Ada] vx7r2cert: port ARM, PowerPC and x86 targets
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5cb0dbd6b19ddc0d569c67fb4346405bf66dedaf;p=gcc.git

[Ada] vx7r2cert: port ARM, PowerPC and x86 targets

gcc/ada/

	* Makefile.rtl: Add vx7r2cert spec file to ARM, PowerPC and x86
	targets.
	* vxworks7-cert-rtp-link.spec: New spec file.
---

diff --git a/gcc/ada/Makefile.rtl b/gcc/ada/Makefile.rtl
index b7df078c0bd..bdaa8056b6b 100644
--- a/gcc/ada/Makefile.rtl
+++ b/gcc/ada/Makefile.rtl
@@ -1136,6 +1136,7 @@ ifeq ($(strip $(filter-out powerpc% wrs vxworks vxworksspe vxworks7% vxworks7spe
     else
       GCC_SPEC_FILES+=vxworks7-rtp-base-link.spec
     endif
+    GCC_SPEC_FILES+=vxworks7-cert-rtp-link.spec
   else
     GCC_SPEC_FILES+=vxworks-$(ARCH_STR)-link.spec
     GCC_SPEC_FILES+=vxworks-cert-$(ARCH_STR)-link.spec
@@ -1411,6 +1412,7 @@ ifeq ($(strip $(filter-out %86 x86_64 wrs vxworks vxworks7%,$(target_cpu) $(targ
 
   ifeq ($(strip $(filter-out vxworks7%, $(target_os))),)
     GCC_SPEC_FILES+=vxworks7-$(X86CPU)-rtp-base-link.spec
+    GCC_SPEC_FILES+=vxworks7-cert-rtp-link.spec
   else
     GCC_SPEC_FILES+=vxworks-x86-link.spec
     GCC_SPEC_FILES+=vxworks-cert-x86-link.spec
@@ -1534,6 +1536,9 @@ ifeq ($(strip $(filter-out aarch64 arm% coff wrs vx%,$(target_cpu) $(target_vend
       GCC_SPEC_FILES+=vxworks-smp-arm-link.spec
     endif
   endif
+  ifeq ($(strip $(filter-out vxworks7%, $(target_os))),)
+    GCC_SPEC_FILES+=vxworks7-cert-rtp-link.spec
+  endif
 endif
 
 # ARM android
diff --git a/gcc/ada/vxworks7-cert-rtp-link.spec b/gcc/ada/vxworks7-cert-rtp-link.spec
new file mode 100644
index 00000000000..0e0440f8ed3
--- /dev/null
+++ b/gcc/ada/vxworks7-cert-rtp-link.spec
@@ -0,0 +1,9 @@
+*self_spec:
++ %{!nostdlib:-nodefaultlibs -nostartfiles}
+
+*link:
++ %{!nostdlib:%{mrtp:%{!shared: \
+     -l:certRtp.o \
+     -L%:getenv(VSB_DIR /usr/lib/common/objcert) \
+     -T%:getenv(VSB_DIR /usr/ldscripts/rtp.ld) \
+   }}}