From: Robert Jördens Date: Fri, 29 Nov 2013 09:20:29 +0000 (-0700) Subject: genlib/coding, test/test_coding: unittests X-Git-Tag: 24jan2021_ls180~2099^2~420 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5ccd1799f2cdd9b1b8f2d7017aabc3f071a726c8;p=litex.git genlib/coding, test/test_coding: unittests --- diff --git a/migen/genlib/coding.py b/migen/genlib/coding.py index ed60e2f3..94a224ea 100644 --- a/migen/genlib/coding.py +++ b/migen/genlib/coding.py @@ -37,15 +37,3 @@ class Decoder(Module): class PriorityDecoder(Decoder): pass # same - -def _main(): - from migen.fhdl import verilog - e = Encoder(8) - print(verilog.convert(e, ios={e.i, e.o, e.n})) - pe = PriorityEncoder(8) - print(verilog.convert(pe, ios={pe.i, pe.o, pe.n})) - d = Decoder(8) - print(verilog.convert(d, ios={d.i, d.n, d.o})) - -if __name__ == "__main__": - _main() diff --git a/migen/test/test_coding.py b/migen/test/test_coding.py new file mode 100644 index 00000000..de098050 --- /dev/null +++ b/migen/test/test_coding.py @@ -0,0 +1,82 @@ +import unittest + +from migen.fhdl.std import * +from migen.genlib.coding import * + +from migen.test.support import SimCase, SimBench + +class EncCase(SimCase): + class TestBench(SimBench): + def __init__(self): + self.submodules.dut = Encoder(8) + + def test_sizes(self): + self.assertEqual(flen(self.tb.dut.i), 8) + self.assertEqual(flen(self.tb.dut.o), 3) + self.assertEqual(flen(self.tb.dut.n), 1) + + def test_run_sequence(self): + seq = list(range(1<<8)) + cur = None + def cb(tb, s): + if seq: + s.wr(tb.dut.i, seq.pop(0)) + i = s.rd(tb.dut.i) + if s.rd(tb.dut.n): + self.assertNotIn(i, [1< 0: + self.assertEqual(i & 1<<(o - 1), 0) + self.assertGreaterEqual(i, 1<