From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 2 May 2019 17:44:59 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xc7mux
X-Git-Tag: working-ls180~1208^2~299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=5cd19b52da297cc7d44e9bf11dc9d1664a02ccce;p=yosys.git

Merge remote-tracking branch 'origin/master' into xc7mux
---

5cd19b52da297cc7d44e9bf11dc9d1664a02ccce
diff --cc techlibs/xilinx/synth_xilinx.cc
index 4ec115bec,8aa7b508e..bde95c638
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@@ -89,86 -74,32 +80,37 @@@ struct SynthXilinxPass : public ScriptP
  		log("    -retime\n");
  		log("        run 'abc' with -dff option\n");
  		log("\n");
 +		log("    -abc9\n");
 +		log("        use abc9 instead of abc\n");
 +		log("\n");
  		log("\n");
  		log("The following commands are executed by this synthesis command:\n");
- 		log("\n");
- 		log("    begin:\n");
- 		log("        read_verilog -lib +/xilinx/cells_sim.v\n");
- 		log("        read_verilog -lib +/xilinx/cells_xtra.v\n");
- 		log("        read_verilog -lib +/xilinx/brams_bb.v\n");
- 		log("        hierarchy -check -top <top>\n");
- 		log("\n");
- 		log("    flatten:     (only if -flatten)\n");
- 		log("        proc\n");
- 		log("        flatten\n");
- 		log("\n");
- 		log("    coarse:\n");
- 		log("        synth -run coarse\n");
- 		log("\n");
- 		log("    bram: (only executed when '-nobram' is not given)\n");
- 		log("        memory_bram -rules +/xilinx/brams.txt\n");
- 		log("        techmap -map +/xilinx/brams_map.v\n");
- 		log("\n");
- 		log("    dram: (only executed when '-nodram' is not given)\n");
- 		log("        memory_bram -rules +/xilinx/drams.txt\n");
- 		log("        techmap -map +/xilinx/drams_map.v\n");
- 		log("\n");
- 		log("    fine:\n");
- 		log("        opt -fast\n");
- 		log("        memory_map\n");
- 		log("        dffsr2dff\n");
- 		log("        dff2dffe\n");
- 		log("        techmap -map +/xilinx/arith_map.v (without '-nocarry' only)\n");
- 		log("        opt -fast\n");
- 		log("\n");
- 		log("    map_cells:\n");
- 		log("        pmux2shiftx (without '-nosrl' and '-nomux' only)\n");
- 		log("        simplemap t:$dff t:$dffe (without '-nosrl' only)\n");
- 		log("        opt_expr -mux_undef (without '-nosrl' only)\n");
- 		log("        shregmap -tech xilinx -minlen 3 (without '-nosrl' only)\n");
- 		log("        techmap -map +/xilinx/cells_map.v\n");
- 		log("        clean\n");
- 		log("\n");
- 		log("    map_luts:\n");
- 		log("        opt -full\n");
- 		log("        techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v\n");
- 		log("        abc -luts 2:2,3,6:5,10,20 [-dff]\n");
- 		log("        clean\n");
- 		log("        shregmap -minlen 3 -init -params -enpol any_or_none (without '-nosrl' only)\n");
- 		log("        techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v\n");
- 		log("        dffinit -ff FDRE   Q INIT -ff FDCE   Q INIT -ff FDPE   Q INIT -ff FDSE   Q INIT \\\n");
- 		log("                -ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT\n");
- 		log("\n");
- 		log("    check:\n");
- 		log("        hierarchy -check\n");
- 		log("        stat\n");
- 		log("        check -noinit\n");
- 		log("\n");
- 		log("    edif:     (only if -edif)\n");
- 		log("        write_edif <file-name>\n");
- 		log("\n");
- 		log("    blif:     (only if -blif)\n");
- 		log("        write_blif <file-name>\n");
+ 		help_script();
  		log("\n");
  	}
+ 
 -	std::string top_opt, edif_file, blif_file;
 -	bool flatten, retime, vpr, nobram, nodram, nosrl;
++	std::string top_opt, edif_file, blif_file, abc;
++	bool flatten, retime, vpr, nocarry, nobram, nodram, nosrl, nomux;
+ 
+ 	void clear_flags() YS_OVERRIDE
+ 	{
+ 		top_opt = "-auto-top";
+ 		edif_file.clear();
+ 		blif_file.clear();
++		abc = "abc";
+ 		flatten = false;
+ 		retime = false;
+ 		vpr = false;
+ 		nobram = false;
+ 		nodram = false;
+ 		nosrl = false;
++		nomux = false;
+ 	}
+ 
  	void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
  	{
- 		std::string top_opt = "-auto-top";
- 		std::string edif_file;
- 		std::string blif_file;
  		std::string run_from, run_to;
- 		std::string abc = "abc";
- 		bool flatten = false;
- 		bool retime = false;
- 		bool vpr = false;
- 		bool nocarry = false;
- 		bool nobram = false;
- 		bool nodram = false;
- 		bool nosrl = false;
- 		bool nomux = false;
+ 		clear_flags();
  
  		size_t argidx;
  		for (argidx = 1; argidx < args.size(); argidx++)
@@@ -219,16 -146,8 +161,16 @@@
  			}
  			if (args[argidx] == "-nosrl") {
  				nosrl = true;
-                 continue;
-             }
+ 				continue;
+ 			}
 +			if (args[argidx] == "-nomux") {
 +				nomux = true;
 +				continue;
 +			}
 +			if (args[argidx] == "-abc9") {
 +				abc = "abc9";
 +				continue;
 +			}
  			break;
  		}
  		extra_args(args, argidx, design);
@@@ -285,86 -197,79 +220,88 @@@
  			}
  		}
  
- 		if (check_label(active, run_from, run_to, "fine"))
- 		{
- 			Pass::call(design, "opt -fast -full");
- 			Pass::call(design, "memory_map");
- 			Pass::call(design, "dffsr2dff");
- 			Pass::call(design, "dff2dffe");
- 
- 			if (!nocarry) {
- 				if (vpr)
- 					Pass::call(design, "techmap -D _EXPLICIT_CARRY -map +/xilinx/arith_map.v");
- 				else
- 					Pass::call(design, "techmap -map +/xilinx/arith_map.v");
+ 		if (check_label("dram", "(skip if '-nodram')")) {
+ 			if (!nodram || help_mode) {
+ 				run("memory_bram -rules +/xilinx/drams.txt");
+ 				run("techmap -map +/xilinx/drams_map.v");
  			}
+ 		}
  
+ 		if (check_label("fine")) {
  			// shregmap -tech xilinx can cope with $shiftx and $mux
 -			//   cells for identifiying variable-length shift registers,
 +			//   cells for identifying variable-length shift registers,
  			//   so attempt to convert $pmux-es to the former
 -			if (!nosrl || help_mode)
 -				run("pmux2shiftx", "(skip if '-nosrl')");
 +			// Also: wide multiplexer inference benefits from this too
 +			if (!nosrl || !nomux)
- 				Pass::call(design, "pmux2shiftx");
++				run("pmux2shiftx", "(skip if '-nosrl' and '-nomux')");
+ 
+ 			run("opt -fast -full");
+ 			run("memory_map");
+ 			run("dffsr2dff");
+ 			run("dff2dffe");
+ 			run("opt -full");
  
- 			Pass::call(design, "opt -full");
- 			Pass::call(design, "techmap");
- 			Pass::call(design, "opt -fast");
+ 			if (!vpr || help_mode)
+ 				run("techmap -map +/xilinx/arith_map.v");
+ 			else
+ 				run("techmap -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
  
- 			// shregmap with '-tech xilinx' infers variable length shift regs
- 			if (!nosrl)
- 				Pass::call(design, "shregmap -tech xilinx -minlen 3");
+ 			if (!nosrl || help_mode) {
+ 				// shregmap operates on bit-level flops, not word-level,
+ 				//   so break those down here
+ 				run("simplemap t:$dff t:$dffe", "(skip if '-nosrl')");
+ 				// shregmap with '-tech xilinx' infers variable length shift regs
+ 				run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
+ 			}
  
- 			if (!nomux)
- 				Pass::call(design, "muxcover -mux8 -mux16");
+ 			run("techmap");
+ 			run("opt -fast");
 +
- 			Pass::call(design, "opt -fast");
++			if (!nomux || help_mode)
++				run("muxcover -mux8 -mux16");
  		}
  
- 		if (check_label(active, run_from, run_to, "map_cells"))
- 		{
+ 		if (check_label("map_cells")) {
 -			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v");
 +			std::string define;
 +			if (nomux)
 +				define += " -D NO_MUXFN";
- 			Pass::call(design, "techmap" + define + " -map +/xilinx/cells_map.v");
- 			Pass::call(design, "clean");
++			run("techmap -map +/techmap.v -map +/xilinx/cells_map.v" + define);
+ 			run("clean");
  		}
  
- 		if (check_label(active, run_from, run_to, "map_luts"))
- 		{
- 			Pass::call(design, "techmap -map +/techmap.v -D _NO_POS_SR -map +/xilinx/ff_map.v");
+ 		if (check_label("map_luts")) {
 -			if (help_mode)
 -				run("abc -luts 2:2,3,6:5,10,20 [-dff]");
 +			if (abc == "abc9")
- 				Pass::call(design, abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
++				run(abc + " -lut +/xilinx/abc.lut -box +/xilinx/abc.box" + string(retime ? " -dff" : ""));
++			else if (help_mode)
++				run(abc + " -luts 2:2,3,6:5,10,20 [-dff]");
  			else
- 				Pass::call(design, abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
- 			Pass::call(design, "clean");
 -				run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
++				run(abc + " -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
+ 			run("clean");
  			// This shregmap call infers fixed length shift registers after abc
  			//   has performed any necessary retiming
- 			if (!nosrl)
- 				Pass::call(design, "shregmap -minlen 3 -init -params -enpol any_or_none");
- 			Pass::call(design, "techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
- 			Pass::call(design, "dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
+ 			if (!nosrl || help_mode)
+ 				run("shregmap -minlen 3 -init -params -enpol any_or_none", "(skip if '-nosrl')");
+ 			run("techmap -map +/xilinx/lut_map.v -map +/xilinx/ff_map.v -map +/xilinx/cells_map.v");
+ 			run("dffinit -ff FDRE Q INIT -ff FDCE Q INIT -ff FDPE Q INIT -ff FDSE Q INIT "
  					"-ff FDRE_1 Q INIT -ff FDCE_1 Q INIT -ff FDPE_1 Q INIT -ff FDSE_1 Q INIT");
+ 			run("clean");
  		}
  
- 		if (check_label(active, run_from, run_to, "check"))
- 		{
- 			Pass::call(design, "hierarchy -check");
- 			Pass::call(design, "stat");
- 			Pass::call(design, "check -noinit");
+ 		if (check_label("check")) {
+ 			run("hierarchy -check");
+ 			run("stat");
+ 			run("check -noinit");
  		}
  
- 		if (check_label(active, run_from, run_to, "edif"))
- 		{
- 			if (!edif_file.empty())
- 				Pass::call(design, stringf("write_edif -pvector bra %s", edif_file.c_str()));
- 		}
- 		if (check_label(active, run_from, run_to, "blif"))
- 		{
- 			if (!blif_file.empty())
- 				Pass::call(design, stringf("write_blif %s", edif_file.c_str()));
+ 		if (check_label("edif")) {
+ 			if (!edif_file.empty() || help_mode)
+ 				run(stringf("write_edif -pvector bra %s", edif_file.c_str()));
  		}
  
- 		log_pop();
+ 		if (check_label("blif")) {
+ 			if (!blif_file.empty() || help_mode)
+ 				run(stringf("write_blif %s", edif_file.c_str()));
+ 		}
  	}
  } SynthXilinxPass;